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Specification Update
AAU63. LBRs May Not be Initialized During Power-On Reset of the Processor
Problem: If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last
Branch Records) may not be properly initialized.
Implication: Due to this erratum, debug software may not be able to rely on the LBRs out of power-
on reset.
Workaround: Ensure that the processor has completed its power-on reset cycle prior to initiating a
second reset.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU64. LBR, BTM or BTS Records May have Incorrect Branch From
Information After an EIST Transition, T-states, C1E, or Adaptive
Thermal Throttling
Problem: The "From" address associated with the LBR (Last Branch Record), BTM (Branch Trace
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an
EIST (Enhanced Intel
®
SpeedStep Technology) transition, T-states, C1E (C1
Enhanced), or Adaptive Thermal Throttling.
Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch
"From" addresses for the first branch after an EIST transition, T-states, C1E, or
Adaptive Thermal Throttling.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU65. VMX-Preemption Timer Does Not Count Down at the Rate Specified
Problem: The VMX-preemption timer should count down by 1 every time a specific bit in the TSC
(Time Stamp Counter) changes. (This specific bit is indicated by IA32_VMX_MISC bits
[4:0] (0x485h) and has a value of 5 on the affected processors.) Due to this erratum,
the VMX-preemption timer may instead count down at a different rate and may do so
only intermittently.
Implication: The VMX-preemption timer may cause VM exits at a rate different from that expected
by software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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