37
Specification Update
AAU66. Multiple Performance Monitor Interrupts are Possible on Overflow of
Fixed Counter 0
Problem: The processor can be configured to issue a PMI (performance monitor interrupt) upon
overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on
overflow of IA32_FIXED_CTR0, however multiple PMIs are observed when this erratum
occurs.
This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and
counter are configured as follows:
•Intel
®
Hyper-Threading Technology is enabled
• IA32_FIXED_CTR0 local and global controls are enabled
• IA32_FIXED_CTR0 is set to count events only on its own thread
(IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0)
• PMIs are enabled on IA32_FIXED_CTR0 (IA32_FIXED_CTR_CTRL MSR bit [3] = ‘1)
• Freeze_on_PMI feature is enabled (IA32_DEBUGCTL MSR (1D9H) bit [12] = ‘1)
Implication: When this erratum occurs there may be multiple PMIs observed when
IA32_FIXED_CTR0 overflows
Workaround: Disable the FREEZE_PERFMON_ON_PMI feature in IA32_DEBUGCTL MSR (1D9H) bit
[12].
Status: For the steppings affected, see the Summary Tables of Changes.
AAU67. VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct
Operand Size
Problem: When a VM exit occurs due to a LIDT, LGDT, SIDT, or SGDT instruction with a 32-bit
operand, bit 11 of the VM-exit instruction information field should be set to 1. Due to
this erratum, this bit is instead cleared to 0 (indicating a 16-bit operand).
Implication: Virtual-machine monitors cannot rely on bit 11 of the VM-exit instruction information
field to determine the operand size of the instruction causing the VM exit.
Workaround: Virtual Machine Monitor software may decode the instruction to determine operand
size.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU68. Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
Problem: Performance Monitor Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA
should only increment the count when a load is blocked by a store. Due to this erratum,
the count will be incremented whenever a load hits a store, whether it is blocked or can
forward. In addition this event does not count for specific threads correctly.
Implication: If Intel
®
Hyper-Threading Technology is disabled, the Performance Monitor events
STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence
of loads blocked by stores than have actually occurred. If Intel Hyper-Threading
Technology is enabled, the counts of loads blocked by stores may be unpredictable and
they could be higher or lower than the correct count.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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