Specification Update 37
Errata
Implication: Due to this erratum, an uncorrected error may be reported and a machine check
exception may be triggered.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ78. PMIs during Core C6 Transitions May Cause the System to Hang
Problem: If a performance monitoring counter overflows and causes a PMI (Performance
Monitoring Interrupt) at the same time that the core enters C6, then this may cause
the system to hang.
Implication: Due to this erratum, the processor may hang when a PMI coincides with core C6 entry.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ79. 2-MB Page Split Lock Accesses Combined with Complex Internal
Events May Cause Unpredictable System Behavior
Problem: A 2-MB Page Split Lock (a locked access that spans two 2-MB large pages) coincident
with additional requests that have particular address relationships in combination with
a timing sensitive sequence of complex internal conditions may cause unpredictable
system behavior.
Implication: This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially-available software.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ80. Extra APIC Timer Interrupt May Occur during a Write to the Divide
Configuration Register
Problem: If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same
time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible
that the APIC timer will deliver two interrupts.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an APIC timer
event.
Workaround:Software should reprogram the Divide Configuration Register only when the APIC timer
interrupt is disarmed.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ81. TXT.PUBLIC.KEY Is Not Reliable
Problem: Intel TXT (Intel Trusted Execution Technology) capable processors, the TXT.PUBLIC.KEY
value (Intel TXT registers FED3_0400H to FED3_041FH) is not reliable.
Implication: Due to this erratum, the TXT.PUBLIC.KEY value should not be relied on or used for
retrieving the hash of the Intel TXT public key for the platform.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ82. 8259 Virtual Wire B Mode Interrupt May Be Dropped When It Collides
with Interrupt Acknowledge Cycle from the Preceding Interrupt
Problem: If an un-serviced 8259 Virtual Wire B Mode (8259 connected to IOAPIC) External
Interrupt is pending in the APIC and a second 8259 Virtual Wire B Mode External
Interrupt arrives, the processor may incorrectly drop the second 8259 Virtual Wire B
Mode External Interrupt request. This occurs when both the new External Interrupt and
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