JVC AX-Z1010TN - K2 Interface and Delay Circuit (VC4111)

AX-Z1010TN
B@VC4111 (}C108): K2 Interface and Delay Circuit
{1) Appearance
2
8
S »
a 62 os 2 -= sc =& # tia OUR a
a ey a aS @aB Fao Begs ia & os
S a 2 2 a @& 2 -e in @B a §
2)
A
33] VSS
[27] soo 26] we
O33) AD? 0 ]38) AD
0 {35} AD3
vc 4111
oO
Le] [2] LE] [E] g
i<a) w a =
e ge edie Togs ee ee ee ee
iy ~ 4
{2} Internal Block Diagem
1/0 1+8
8 Bit 8 Blt
$01 Oata Register Data Register 5p0
snift Register Snift Régister
Data tatch
Clock
spsy Out
WC Oye
slo O«t
1/0 Control
cE Ont Timing
oe Ou Generator
Wwe ©
|_| [YO avo~10
SRAM
BCcO
Adress
he——-E) TsTc
Generator
RESET Ome
Test Clock
x BCO Test control
Generator Logic
i} Mode h————O s1
CSMODE C
Selecter S2
1-26 (No. 20115)