JVC AX-Z1010TN User Manual

(3) Pin Description
AX-Z1010TI
Pin No.| Pin Name vo L Function
1 VSS - GND
2 AD8 oO
SRAM memory address signal output pins
3 | aps oe Ue Y eee
4 WE fe) SRAM memory WE signal output pin
5 OE fe) SRAM memory OE signal output pin
6 AD10 oO SRAM memory address signal output pin
7 CE (e) SRAM memory CE signal output pin
8 vos V0
SRAM memory data signal |/O pi
9 vO7 1/0 my See ee
10 vss - GND
11 vO6 vO
12 Vos 1/0
13 04 VO
SRAM memory data signal 1/O pins
14 VvO3 vO
15 Vvo2 vo
16 01 0
17 $2 1
| LSI operation mode select input pin
18 $i (CMOS)
Selection
Fs = 44.1 kHz selected
Test mode
8 kHz selected
H Ps = 32 kHz selected
19 RESET I(CMOS)} | LSI reset input pin, The LSI is initialized with RESET “’L”.
20 vSs - GND
21 VDD -_ Supply voltage
22 sol HCMOS) | Serial data input pin.
The data synchronized with the fail of the BCO clock is input in the MSB first mode.
23 BCO O(CMOS) | Serial data shift clock output pin
24 SDSY O(CMOS} | Fs signal {sampiing frequency) output pin
25 SLD 0 At the rise of the WC output signal, outputs an ‘’L’’ signal with a width of two clock pulses in syn-
chronization with the rise of the BCO clock.
26 WC ie) Outputs the 2Fs signal synchronized with the Fs signal.
27 spo Q Serial data output pin
Outputs the serial data previous 10 msec and read from the SRAM, in the MSB first mode in syn-
chronization with the fall of the BCO clock.
28 Xl HKCMOS) | Clock input pin
23
30
TSTC 1{CMOS)
Input pin to select the test status of the address counter in the LSI when the test mode is engaged.
Input pin to select the LSI operating condition.
31
32
33
34
35
36
37
38
39
CS MODE] KCMOS)
apo | 0
AD1 fe)
vss _
AD2 fo)
AD3 fe)
AD4 fe)
AD5 fe)
AD6 fe)
AD? fe)
VDD
4
SRAM memory address signal output pins
GND
SRAM memory address signal output pins
Supply voltage pin
{No. 20115) 1-27

JVC AX-Z1010TN Specifications

General

Brand	JVC
Model	AX-Z1010TN
Category	Amplifier
Language	English