JVC GR-DA30UC - MAIN REG Interconnection

(No.YF219)2-21 2-22(No.YF219)
yf219_y10716001a_rev1.1
MAIN(REG)
10
R6102
OPEN
Q6701
RSR025P03-X
D
G
S
R6712
560
C6403
1
C6707
REGRTC_OUT
D6101
RB521S-30
C6102
10
TL6004
C6706
220p
TL6009
L6501
NQL52EM-221X
C6001
1
C6008
1
R6407
22kΩ
R6502
2.7k
LITHIUM
R6408
10kΩ
R6519
150K
TL6001
C6303
0.068
REG_2.8V
C6201
0.1
D6504
1SS355
R6401
ADP_DC
C6203
OPEN
L6701
NQL52EM-390X
C6505
1
12k
R6304
R6306
#
TL6003
R6403
470kΩ
SYS_RSTL
R6802
18k
R6702
0.2
0.25W
NRV142F-R20X
R6714
470
R6014
27k
D6701
RB160M-30
C6401
OPEN
LIT_2.8V
C6305
#
C6009
1
R6512
3.9k
L6301
NQL62EM-470X
M_UNREG
R6007
100k
R6716
20k
R6514
6.8k
REG_-7.5V
R6005
C6007
OPEN
R6013
10k
D6201
RB521S-30
C6701
1
CAP_PWR
R6201
OPEN
C6405
#
C6104
OPEN
C6402
1
C6504
1
R6203
OPEN
R6101
47k
L6801
NQL79GM-470X
R6719
AL_2.8V
Q6401
US5U29-W
1
G
2
S
3
A
4
CA
5
D
C6506
1
DRUM_ERR
R6010
D6703
RB160M-30
REG_1.2V
C6202
10
R6801
L6201
NQL87EN-390X
C6704
4700p
I_MTR
TO CPU
C6204
220p
C6502
1
R6717
R6404
10kΩ
GND
TL6006
L6001
NQL382M-100X
R6006
R6206 OPEN
C6802
10
GND
D6503
1SS355
C6002 1
C6501
1
R6721
CHRG_EVR
L6101
NQL87EN-390X
C6509
0.033
TL6011
R6105
C6301
1
M_REG4.65
REG_CS
R6104
OPEN
IC6001
FA7760AF
65
R6303
100k
R6204
100k
D6505
1SS355
C6003
OPEN
R6715
5.1k
C6703
OPEN
TL6005
Q6301
US5U29-W
1
G
2
S
3
A
4
CA
5
D
BAT_H
L6702
OPEN
R6307
47k
C6302
1
C6801
470p
C6004
1
BATT_+
TO MAIN IF(CN101)
R6301
D6002
RB551V-30-X
D6506
1SS355
R6406
#
R6202
OPEN
R6205
CAP_ERR
C6304
0.1
C6006
1
R6305
10k
REG_4.65V
L6502
C6101
0.1
TL6007
R6718
C6404
0.01
D_GAIN
R6106 1M
D6507
UDZS8.2B-X
R6723
120k
C6702
10
C6510
0.1
Q6505
2SA1774/QR/-X
DRUM_PWR
D6801
RB551V-30-X
R6709
110k
IC6001
FA7760AF
49
OUT3P
50
PGND1
51
OUT1
52
OUT1S
53
PVCC1
54
OUT5
55
PVCC5
56
SW7-1
57
SW7-2
58
SWI-1
59
SWI-2
60
SW6
61
PVCC2
62
OUT2
63
PGND2
64
OUT2S
1OUT11 2VIN2 3IN2- 4FB2 5OUT12 6VIN1 7IN1- 8FB1 9FB8
10IN8- 11IN8+ 12IN6- 13FB6 14IN7- 15FB7 16IN5-
17
FB5
18
OUT10
19
VIN5
20
IN8H-
21
IN8H+
22
IN3+
23
IN3-
24
FB3
25
IN4+
26
IN4-
27
FB4
28
VREF
29
VREG
30
VIO9
31
VCC
32
TBI
33 BAT_H 34 VDD 35 RSTO 36 SEL9 37 CLK 38 GND 39 RT 40 IN9- 41 FB9 42 CS 43 DATA 44 OUT9 45 PVCC3 46 PGND3 47 OUT6P 48 OUT4P
R6103
OPEN
REGRTC_CLK
C6503
1
C6705
0.01
R6708
15k
C6803
100p
L6401
NQL62EM-470X
REG_15V
R6308
5.6k
T_BATT
C6005
1
TL6002
C6103
220p
R6713
100k
L6002
NQR0351-001X
820p
220µ
0Ω
39µ
47µ
39k
47µ
300k
1k
0Ω
20k
10µ
120k
0Ω
10
0Ω
10
22µ
0Ω
47µ
TO MAIN IF(CN101),CPU
TO CPU
TO MDA
TO MDA
TO MDA
TO CPU
TO CPU
TO MAIN IF(CN101)
TO CPU
!
!
!
MAIN(REG) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
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