JVC KD-LX50R - Page 26

Vcc WP SCL SDA
A0
A1 A2
GND
A0 1
A1 2
A2 3
GND 4
8 Vcc
7 WP
6 SCL
5 SDA
32k bit EEPROM ARRAY
12bit
12bit
ADDERESS
DECODER
SLAVE/WORD
ADDRESS REGISTER
8bit
DATA
REGISTER
ACK
START
STOP
CONTROL LOGIC
HIGH VOLTAGE GEN.
Vcc LEVEL DETECT
Vcc
GND
AO,A1,A2
SCL
SDA
WP
-
-
IN
IN
I/O
IN
Power supply
Ground (0V)
Slave address set
Serial clock input
Slave and word address/Serial data output
Write protect input
Pin No. I/O Functions
BR24C32F-X (IC703) : EEPROM
1. Pin function
2. Block diagram
3. Pin function