JVC MX-DVB10 - Page 65

MX-DVB10
1-65
1. Pin layout
3. Pin function
1. Block diagram
MM3023DN-X (IC1, IC102) : Switching regulator
2
5
4
3
1
VOUT
VDD
GND
NC
CE
10k
Vref
Current Limit
GND
CE
V
DD
V OUT
5
3
1
2
Pin No. Symbol I/O Function
1
2
3
4
5
GND
VDD
VOUT
NC
CE
Connect to GND
Power supply
Regulator output
No connect
Output voltage on/off control
-
-
O
-
I
1
2
3
4
8
7
6
5
NC
VCC
CS
SK
NC
GND
DO
DI
2.Pin Functions
BR93LC66F-X (IC403) : EEPROM
1. Pin layout
Symbol
VCC
GND
CS
SK
DI
DO
I/O
-
-
I
I
I
O
Power supply
Connect to GND
Chip select input
Serial clock input
Start bit,OP-code,address,serial data input
Serial data output,
Internal state display output of READY/BUSY
Function
INSTRUCTION
REGISTER
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
ADD.
BUFFERS
DATA
REGISTER
16
R/W AMPS
AND
AUTO ERASE
16
DECODER
EEPROM
4096bit
256 x 16
VPP SW
VREF
VPP
GENERATOR
DO
DI
CS
SK
PE
2. Block diagram