JVC SR-DVM700EU - Page 56

A
1
2
3
4
5
BCDEFG
IC1801
PHY_LPS
CN1801
R1818
L1801L1802 C1804
RA1801
C1805
C1803C1806
PHY_CTL[0]
X1801
RA1802
B1801B1802
D3.3V
R1820
PHY_CNA
K1801
C1813
C1810
R1801
PHY_DATA[0-7]
PHY_CTL[1]
PHY_CLK
PHY_LINK_ON
PHY_RESET[L]
R1802
R1819
PHY_LREQ
C1814
GND
T1803T1803
T1804T1804
T1803T1803
T1804T1804
CN1802
T1801T1801
T1802T1802
T1801T1801
T1802T1802
R1805
R1810 R1806
R1812
R1808 R1807 R1809
C1801
R1821 R1811
C1808
R1822
C1809
C1807
C1811
C1812
R1826 R1825 R1824 R1823
R1827 C1816 C1815
R1813 R1814 R1815 R1816R1817
C1802
R1803 R1804
p30128001a_rev0
SHEET 6
IEEE1394 section
TO SHEET 4
TO CN7121
SHEET 23
NOT USED
2-15 2-16