Kenwood TR-2600A - Page 7

TR-2600A/E
CIRCUIT DESCRIPTION
Rating ;
item Symbol Condition Twin. St. St. Tmax. | Unit
Vi (off) | Ver = 5V, lo=100uA| — | — | 0.
Input voltage +
V1 (on) | Vo =0.3V,lo= 2mA | 3.0 | — - Vv
Qutout voltage | Vo fon) | lo=10mA,li=0.5mA| — [0.1] 03 | V
| Input current li V1 =5V rT
Output current | lo (off) | Vec = 30V, V1 = OV
| OC current gain Gl lo = 5mA, Vo = 5V 68 | —
Input impedance R4 _ 47
1/0 impedance
Table 8 DTC144ES Electrical characteristic (TX unit 7,16)
@ PLL IF section
The superheterodyne oscillator employs third overtone
crystal oscillators. During low frequency band reception
(140.000 to 149.995MHz), X2 (42.6MHz) oscillates via
Q13 : 2SC2347, at an output frequency of 127.8MHz, and
during high frequency band reception (150.000 to 159.995
MHz), X3 (45.933MHz) oscillates with an output frequency
of 137.8MHz. The T,W,M2 and X model types are factory-
preset so only the low band crystal oscillator X2 operates.
The PLL IF, after mixing with the VCO output at Q14:
2SC2668, is factory-set (No over-range capability) as
follows:
Type RX/TX Frequency
| Panes ss oom
K
M1
RX
156
—
11.495MHz
: TX 14.2) — 21.195MHz
ee a 9.495MHz_|
: TX 16.2 —- 20.195MHz |
M3 RX 1.5 —-— 11.495MHz
TX 12.2. — 22.195MHz
T.W RX 5.5 — 7.495MHz
TX 16.2) — 18.195MHz
Table 9
DCL UNIT (X57-1110- 10)
The Digital Coded Squetch (DCS) circuit consists of 1C3
slave microprocessor : uPD7507G, IC2 modem : MN6127A
and {C1 op amp : NJM4558M. Pin assignments of |C2 and
iC3 are shown in Tables 10 and 11. The uPD7507G micro-
processor clock operates at approximately 200kHz (pin
5&9 (CL1, CL2}) and is internally divided by 2 to operate
at approximately a 10sec. machine cycle.
@ DCS Reception operation
A
received
signal
supplied
from
the
RX
unit
(X55-1380-X
X)
audio
stage
is
amplified
by
|C1
to
approximately
a
0.35V
input
jevel
for
the
modem,
and
is
then
input
to
pin
5
(Ri)
of
the
modem,
In
the
modem,
the
MSK
(Minimum
Shift
Keying)
modulated
input
signal
is
bandpass
filtered
to
at-
tenuate
any
of
out-band
noise,
and
is
then
demodulated
to
an
NRZ
(Non
Return
Zero)
signal
by
delay
detection.
The
demodulated
signal
is
output
to
pin
25
(RD)
and
the
play-
back
clack
(1200
baud}
is
output
to
pin
26
(RT).
IC2
outputs
data
to
RD
at
the
jeading
edge
of
RT.
At
the
leading
edge
of
RT,
IC3
interrupts
INTO
and
retrieves
data
from
[C2
RD
to
IC3
P10.
During
this
time,
frame
sync
detection
(15
bits)
is
performed.
Once
all
15
bits
coincide,
the
Hagelburger
decode
processing
begins.
As
completion
of
the
decoding
process,
a
check
is
performed
to
ascertain
whether
the
frequency
data
(See
Table
12)
is
decimal
or
all
F
(Hexadecimal).
MTC
(pin
25
(P40})
is
then
sent
high
to
transfer
data
to
the
microprocessor.
The
master
microprocessor
always
detects
communication
requests
from
the
slave
microprocessor;
if
it
detects
a
communications
request
(MTC
=
High),
the
master
microprocessor
retrieves
data
at
an
8
bit
preset
data
length
via
serial
interface
(SCK,
S$!
and
SO).
The
input
data
is
pro-
cessed
according
to
the
DCS
system
conditions.
® DCS Transmission operation
In
opposition
to
reception
mode
operation,
when
the
master
microprocessor
detects
the
transmission
mode,
it
brings
the
transmission
request
line
CTM
(pin
43
(P12))
to
{C3
high.
Upon
detection
of
this
transmission
request,
1C3
retrieves
data
via
the
serial
interfaces.
When
all
data
is
retrieved,
|C3
performs
Hagelburger
encode
processing,
at
the
completion
of
which
!C3
makes
the
ME
line
(pin
29
(P43))
high
and
modulator
enable
ME
(pin
21)
active.
Because
IC2
retrieves
the
level
at
the
SD
pin
at
the
leading
edge
of
the
transmission
clock
(ST
pin),
and
in
order
to
lock,
{C2
interrupts
using
INT1
at
the
leading
edge
of
the
ST
pin,
thus
allowing
data
to
be
transferred
from
P42
to
the
SD
pin
during
this
interrupt
routine.
1C2
is
capable
of
obtaining
the
MSK-modulated
signal
by
sync-inputting
the
NRZ
signal
in
lock
with
the
transmission
clock.
When
data
is
to
be
transmitted,
all
the
frequency
data
should
be
F
(Hexadecimal).
@ Reset function
Since slave microprocessor IC2 does not have any data to
be
backed
up
in
RAM,
no
back-up
is
performed.
Therefore,
because it is always necessary to reset when power is
switched on, this is automatically achieved by means of a
reset circuit consisting of lambda diode D3 : MA522(Q)
and
Q1
:
28C2712(Y).
The
reset
switch
on
the
main
unit
permits manual resetting as well.