152 Keysight X-Series Signal Generators Error Messages
Error Messages
List of Error Messages
804 Digital module input FIFO underflow error; There are not enough samples
being produced for the current clock rate. Verify that the digital
module clock is set up properly.
This error is reported when the digital module clock setup is not
synchronized with the rate the samples are entering the digital
module. Verify that the input clock rate matches the specified
clock rate under the clock setup menu.
805 Digital module output FIFO overflow error; There are more samples being
produced than can be consumed at the current clock rate. Verify that
the digital module clock is set up properly.
This error is reported when the output FIFO is overflowing in the
digital module. This error can be generated if and external clock
or its reference is not set up properly, or if the internal VCO is
unlocked.
806 Digital module output FIFO underflow error; There are not enough
samples being produced for the current clock rate. Verify that the
digital module clock is set up properly.
This error is reported when the output FIFO is underflowing in the
digital module. This error can be generated if and external clock
or its reference is not set up properly, or if the internal VCO is
unlocked.
807 Unexpected digital module interface FPGA; The instrument FW is not
compatible with the interface FPGA on the digital module
(0x{code},0x{code}). The supported FPGA version and code revision is
(0x{code},0x{code}). To ensure proper operation, please refer to the
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