DSS-1

Korg DSS-1 Service Manual

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2.

Producing

timing

and

addresses

for

the

DRAM

(256

K

bits

x

12)

The

above

clocks

TO

to

T15

are

input

from

the

GA-I

DMA

request

clock

input

terminals

DREQO

to

DREQ15.

A

16-channel

DMA

request

received

by

GA-I

is

en

coded

by

addresses

used

to

specify

3

channels

(CHO

to

CH2)

and

three

GA-n

chip

select

signals.

Channels

0

to

7

are

processed

by

CSL1

and

chan

nels

8

to

15

by

CSL2.

CSL3

uses

the

IC15

NAND

as

the

ROW

address

for

refreshing.

GA-n

processing

is

done

by

outputting

an

acknowledgment

(ACK)

cor

responding

to

the

DREQ

channel

on

GA-I

timing,

specifying

the

address

in

memory

by

address

infor

mation,

and

incrementing

the

address

(DMA

AD

DRESS

CONTROL).

3.

Transfer

of

PCM

DATA

read

out

by

the

DMA

from

the

DRAM

to

CPU

1

PCM

data

are

latched

from

CPU

1

to

the

DRAM

by

the

respective

interface

circuits

listed

below,

then

connected

to

the

data

bus.

To

the

DAC,

among

the

12

bits

from

SDO

to

SD11

the

low-order

6

bits

from

SDO

to

SD5

pass

through

the

logic

HC

08

(IC17

and

IC18)

for

resolution

to

be

latched,

then

are

connected

to

the

12-bit

DAC

BA9221

(IC37).

D/A

resolution

is

for

the

purpose

of

controlling

the

resolution

of

the

reproduced

sound

and

is

controlled

by

CPU

1

(panel

switch

parameter

16).

4.

SAMPLE

AND

HOLD

(S/H)

The

DAC

signal

output

type

is

converted

from

current

type

to

voltage

type

by

OP

AMP

5534

(IC38).

This

output

contains

a

mixture

of

16

channels,

so

S/H

is

performed

for

each

channel

by

the

ACK

signal

pro

duced

by

GA-n,

the

high-speed

analogue

switches

(HC4066)

of

IC41,

IC44,

IC47

and

IC50,

and

the

OP

AMP.

Connectors

CN49

and

CN50

can

observe

wave

forms;

S/H

is

performed

again

by

KLM-1061

and

noise

is

removed

(the

CLOCKs

are

T2

to

T15

and

DR1).

5.

Audio

input

signal

control

The

signal

that

is

input

for

sampling

from

connector

CN15

enters

the

filter

circuit

(panel

control

by

CPU

1)

with

the

GAIN

and

ATT

determined

by

IC64.

This

filter

circuit

is

an

LPF

formed

by

operational

amplifiers

IC67

and

IC68;

the

frequency

is

20

kHz.

IC67

and

IC70

form

an

absolute

value

circuit

the

out

put

of

which

is

read

into

CPU

2

as an

LCD

level

meter.

IC58

and

IC63

produce

a

trigger

which

starts

sampl

ing.

The

transition

from

"H"

to

"L"

is

observed

at

the

start

of

sampling

by

connector

CN12A-9.

While

the

level

is

"H",

GA-I

Do

to

D6

DATA

are

not

read

into

GA—I

(GH).

IC54, IC55,

IC56

and

IC57

form

SAR

(Successive

Ap

proximation

Registers).

4.

KLM-783

This

circuit

board

consists

of

the

DSS-1

VCF

and

VCA

sections,

and

equalizer

and

noise

generator

sections.

Its

outline

is

as

follows.

The

VCF/VCA

circuit

employs

8

custom

IC

NJM2069BDS

(IC101

to

IC801)

and

operates

upon

receiving

control

voltage

(CV) from

CPU

2

(KLM-781).

ICM5201

(IC102

to

IC802)

selects

the

VCF

output

format

with

software,

selects

12

dB/OCT

or

24

dB/OCT

and

in

puts

VCF

output

to

the

2069

VCA

INPUT

terminal.

Voice

processing

of

the

MULTIPLEX

CVs

from

CPU

2

is

performed

by

the

following

respective

exclusive

multi

plexers:

VCF:

IC9

(4051)

output

voltage

±5V;

IC5

and

IC6

(M5224)

form

the

S/H.

VCA:

IC8

(4051)

output

voltage

0

to

10V;

IC3

and

IC4

(M5224)

form

the

S/H.

■NOISE,

RESONANCE

OSC

MIX

RATIO

and

so

on

for

the

other

CVs:

IC7

(4051)

output

voltage

0

to

10V;

IC1

and

IC2

(M5224)

form

the

S/H.

The

VCA

output

for

each

voice

is

mixed

by

a

mixer

cir

cuit

(IC15),

enters

the

equalizer

TC9156P

(IC16)

con

trolled

by

CPU

2;

then

equalizing

processing

is

per

formed

and

the

result

is

output

from

OP

AMP

4558

(IC14).

The

noise

generator

is

formed

by

transistor

2SC2785

selected

and

OP

AMP

4558

(IC12).

The

noise

VCA

cor

responds

to

transistors

Q1

and

Q2,

and

operational

amplifier

4558

(IC13).

5.

KLM-786

This

circuit

board,

which

forms

the

power

supply

circuit,

consists

of

the

following.

1.

Regulators

7805

(IC1)

and

7905

(IC2)

this

is

a

±

5V

power

supply

used

principally

for

VCFA

and

DDL.

2.

Regulators

7812

(IC3)

and

7912

(IC4)

this

is

a

±12V

power

supply

used

mainly

for

the

operational

amplifiers.

3.

Regulators

7812

(IC5)

this

is

a

+

12V

power

supply

used

for

the

FDD

motor.

4.

Power

transistor

2SB533

(Q1)

this

is

a

+

5V

2.5A

power

supply

used

for

the

digital

system.

41

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Table of Contents

Other manuals for Korg DSS-1

Owner's Manual312 pages

User Guide16 pages

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Korg DSS-1 Specifications

General

Brand	Korg
Model	DSS-1
Category	Synthesizer
Language	English

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