Korg DSS-1 Service Manual

2. KLM-781
KLM-781 is a CPU2 board.
The CPU2 is 8 bit Microcomputer HD63B03X (IC11) and
each port function is as follows.
Additionally Program ROM (IC15) is 16K byte, Work
RAM (IC14) is 8K byte.
■CPU2 PORT FUNCTION
Port P20 CV, S/H Channel control Output Port
Port
P21 CV, S/H Channel control Output Port
Port P22 CV, S/H Channel control Output Port
Port P23 MIDI IN
PortP24 MIDI OUT
Port P25 CV, S/H INHIBIT 0 - 2 Output Port
Port P26 CV, S/H INHIBIT 0 - 2 Output Port
Port P27 CV, S/H INHIBIT 0 - 2 Output Port
Port P54 PROGRAM UP (by FOOT SW) Input Port
Port P55 DAMPER (by FOOT SW) Input Port
Port P60 A/D Input Channel control Output
Port P61 A/D Input Channel control Output
Port P62 A/D Input Channel control Output
Port P63 VCF MODE (24dB/OCT, 12dB/OCT switch)
PortP64 SERIAL CONTROL CLOCK
PortP65 SERIAL CONTROL DATA
Port P66 EQ, DDL1 LEVEL STB
Port P67 DDL2 INPUT SELECT
By Keyboard Scan, lower address (A0 - A3) 4 bit is
latched at IC9 (HC77), and is decoded at IC6, IC7
(HC138) and is output to Keyboard Matrix. IC6 is to out
put address for the first contact, and IC7 is to output ad
dress for the second contact.
Keyboard data, such as Note Data, key Velocity Data are
read to CPU2 after through Octal Buffer HC240 (IC5).
CV for VCF/A (KLM-783) latches Data Bus DO - D7 at IC12
(4 bit) and IC13 (8 bit) to control 12 bit DAC BA9221 (IC16).
Also, Reference voltage (15V) at DAC is generated at
OP AMP 4558 (IC19).
Analog voltage of Slide VRs on the panel goes through
Multiplexer 4051 (IC 3) and is converted A/D by CPU2.
IC4 is two-way Data Bus Buffer IC and constructs Interface
Circuit with CPU 1.
3. KLM-782
KLM-782 is combined with the SAMPLE AND HOLD
(S/H) circuit board KLM-1061 to form the DSS-1 TONE
GENERATOR (TG) section. The block configuration is
as shown in Fig. 1.
IOUTUNE OF FUNCTIONS
. Creation of DMA request clock in accordance with
command from CPU 1.
ICs 1,2, 3,6,7 and 8 are CMOS programmable inter
val timers which have 3 independent 16-bit counters
inside one chip. In combination with the custom gate
array /^PD65011C-023 (GA-ffl) (IC4, 5) predivider,
they form a 19-bit divider. The master clock is 32
MHz. TO to T17, which are produced from it, are rec
tangular waveforms with approximately 50% duty
cycles. The frequencies of TO to T15 vary from 64 Hz
to 64 kHz depending on conditions and determine the
musical intervals.
T16 is the ADC system clock with a frequency of
about 500 kHz. T17 is a clock with a frequency of
about 31 kHz for refreshing DRAM.
TO and T1 are the EOC of ADC respectively. In com
bination with CPU WRITE (Y7), CPU READ (Y14)
and the logic formed by IC59, IC60, IC61 and IC62,
become DREQ0 and DREQ1 signals only when
selected.
Fig. 1
CPU-1 Adrs Bus
Data Bus
CN-10, 11
OREQ
GEN
GAIN
ATTN
H
DMA
TIMING
CNTRL
IC 11
ADDRESS
CNTRL
IC 12,13
WE
RAS
CAS
IC25-36
256K DRAM
Ac
-A8
PCM DATA
BUS
Latch ft
Resolution
INPUT
SIGNAL
IC 64. 65. 66
IC 17. 18
21.22
h
IC 37
38
J_L
IC41.44, 47, 50
40. 42, 43, 45, 46, 48, 49. 51
S/H x 16
KLM-1061
S/H x 16
TO-
To VCFi, A
40
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Korg DSS-1 Specifications

General

Brand	Korg
Model	DSS-1
Category	Synthesizer
Language	English