Korg DW-8000 - Page 34

CPU
63B03X
PIN
CONFIGURATION
BLOCK
DIAGRAM
VssjT
r
o
,
Vss
He
XTAL(T
MjFtg
t»
1#
{Tin)
—
-
EXTAL
(T
62j
WR
P,, (Tout!)
—
MP
0
(T
|r/W
p„!SCLK)~-
MP,
OE
-
r¥5[6
liJ
BA
p
i
»
(Tout2)
«•—
ST
§Y (T
HjDc
P„{To
U
t3»—-
nmiQT
13
D,
p
,,n-CLK>_j-
P
2
o[9
Hdj
Qo
Hd
3
p«cn
13
p»Q2
5U
Os
Pu
(13
53
Pl5{jl
13
o
7
Pi6
(]J5 501
A
0
p
I7
(H
63B03X
lA,
Pjo0
1a
2
Psi
M
13
As
P52^
Ha*
l
H)Aj
44lA
6
p
55
m
m
a?
p
tt
(jwQ
t
)
P56^
42)
Vss
p,
j
<i?rcr
3
>
p
57
m;
43
a*
p
.><
MR
>
p«,m;
lA,
P
6
1
HI
M|ai0
p*
,
p«Hz
1
A,J
p
,.
Pas
[28
33
a
12
p
’
7
p»m
31
All
P6s(30
U
Am
p
40
P
66
||T
34} Aij
p.,
P
6i
(32
lv
cc
J-\
5)
Panel
switch
scanning
In similar
fashion to
keyboard
scanning,
2-bit
addresses
in the range
AO^AI
are
decoded by
the
address
decoder
LS1
139
(IC18)
and
supplied to
the
switch
matrix.
The
output
goes to
octal
buffer HC240 (1C16)
(the
same
as
used
by the
keyboard) and
is
passed
to
the
data
bus.
6)
LED
Display
The
LED
display
is
software
controlled.
Latch
HC374
(IC22,
IC24)
takes
LCD display
data
from
the
D0~D7
8-bit
data
bus
to
operate
LED
drivers
54513
and 54562.
7)
Digital
delay
The KLM-775
board
has
its
own
dedicated
delay
gate
array,
/iPD65010CW-1
13.
The delay
circuit
comprises this
gate
array,
64KB dynamic
RAM x
2,
ADC,
DAC,
and
analog
compander.
The delay
time
can
be
specified.
CPU
63B03X
STATE
OF
PORT
Port
Pin
Function
P20 9
Velocity
Sens.
Control 3 Bit
P21 10
Velocity
Sens.
Control 2
Bit
P22
11
Velocity
Sens.
Control 1
Bit
P27 16
Velocity Sens.
Control 0
Bit
RX
12
MIDI
RX
TX
13
MIDI
TX
P25
14
TAPE
OUT
P26
15
TAPE
OUT
IRQ1
17
Arpeggio
Clock
P51
18
Joy
Stick -Y or
+Y
P52
19
A/D
Compare
P53
20
+5
P54
21
Portamento
Pedal
P55
22
Program
Up
Pedal
P56
23
Damper
Pedal
P57
24
TAPE IN
P60
25
DWGSFREQ. DATA
D15
P61
26
DWGS
FREQ.
DATA
Dl4
P62 27
DWGSFREQ. DATA
D13
P63
28
DWGS FREQ. DATA
D12
P64
29
DWGSFREQ. DATA
Dll
P65
30
DWGSFREQ.
DATA
DIO
P66
31 DWGS
FREQ. DATA
D 9
P67
32
DWGS
FREQ. DATA
D 8
-
37
-