Korg Poly-800II - Page 25

5
6
ITEM
POLY-800II
POLY-800
DATA BACKUP
SEQ MODE
SEQ CLOCK
INT/EXT
MIDI CHANNEL
PROG CHANGE
One-time Back
repeat
Back up
Back up
Back up
Not available
INT fixed at power ON
Back up
Disable at power ON
MIDI SPECIFICATIONS
CHANNEL
MODE MESSAGES
DATA DUMP
Channel selection available in SEND or
RECEIVE, however SEQ data fixed at CH 2.
OMNI ON until parameter 87 is called.
Reception only OMNI ON/OFF
SEND/RECEIVE OF DATA DUMP
Channel selection available only at RECEIVE.
Note data fixed at CH 1, SEQ data at CH 2.
OMNI ON until parameter 86 is called.
Sends OMNI OFF, POLY ON at SEQ START
Sends OMNI ON, POLY ON at SEQ STOP
Not available with POLY-800 alone.
2. MAIN CIRCUIT EXPLANATION
KEYBOARD DATA PROCESSING AND PANEL SWITCH OPERATION
There are six 8-tone keyboard buses (plus 1 tone for high C).
IC34 decodes addresses for CPU bus line supply.
Key on/off data is read by the CPU via the IC33 buffer.
When the CPU receives key data, it instantly outputs pitch
data to the TG. (Tone Generator)
Note: If IC34 (TC40H138) fails, then there will be no sound for
some of all groups of eight notes. If IC33 (TC40H240) fails
then sound will not be heard for every eighth note.
Switch operation is exactly the same as the keyboard.
DC01 and DC02 octave switching is read by the CPU via
matrix circuit and performed by IC3 (MSM5232) itself. The
MSM5232 output goes through waveform synthesis circuit
(which includes IC's 4, 5, and 6) and is input to filter chip IC1
(NJM2069).
Likewise, EG (DEG1, DEG2, DEG3), LEVEL1, LEVEL2,
CUTOFF, and other switching is read by the CPU via the
same matrix. The CPU processes the data and controls
IC2069 via a D/A converter and time sharing CV circuit.
Data of sounds created by the user is stored in static RAM
KLM-779 IC20 (MPD4464). Therefore, to maintain all program
data when the unit is turned off, it is necessary for this type of
memory to have a battery have a battery backup. Although
the system does contain a built-in lithium battery to protect
the memory, it is housed in the main circuit board KLM-1032
— not in KLM-779 which contains the RAM. Consequently, if
the KLM-779 is disconnected, timbre data will be erased.
As for the delay circuitry, a Gate Array (MPD65010 CW-113),
such as is used in the DW-8000 is used for digital delay, pro
viding delay according to signal specified time (max. of 1024
seconds).
The DRAM for external connection is 256Kbit.
The Digital Delay and Equalizer circuitry are controlled by lat
ched data of IC25 (74HC174) which is connected to the DATA
BUS from the main circuit board KLM-1032 CPU. This control
is carried out via FET switches F1 and F3 ON/OFF control of
Digital Delay parameter settings, EQ parameter setting and
Digital Delay circuitry.
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