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5
4
4
3
3
2
2
1
1
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C C
B B
A A
Size Document Number Rev
Date: Sheet of
Reproduction without the express written consent of Young Chang Co., Ltd. is prohibited.
By
Title
021402 DV2-A
RP2A ENGINE BOARD - SP4x Configuration
Young Chang R&D Institute
1432 Main St.
Waltham MA 02451
Friday, January 07, 2011
USA
Copyright 2010 Young Chang Co., Ltd.
R. Folk
MARA CLOCK, DELAY MEMORY, SCAN PORT, CPLD
35
FUNC GEN
ARPY
CPLD
BiDir
Xilinx Parallel Cable
DDR RAM
SCAN PORT INTERFACE
OSC DISABLE
Place Circuit Close to SH-2A ADC pins
Connect to SH-2A AVREF pin
(SPANA_OUT2)
VCC33
VCC25
VCC25
VCC25
VCC25
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
-12V
+12V
VCC33
C111
0.1uF
C111
0.1uF
12
C110
0.1uF
C110
0.1uF
R101
0
R101
0
C108
0.1uF
C108
0.1uF
U7B
NC7WZ125
U7B
NC7WZ125
5 3
7
U8
74HC245
U8
74HC245
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
OE
19
DIR
1
B0
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
VCC
20
GND
10
R41
1.00K
R41
1.00K
R36
33
R36
33
L14
600 OHM @ 100MHz
L14
600 OHM @ 100MHz
R42
10.0K
R42
10.0K
R45 22R45 22
C117
0.1uF
C117
0.1uF
RN24
10K
RN24
10K
1
2
3
4
8
7
6
5
RN27 150RN27 150
1
2
3
4
8
7
6
5
C116
0.1uF
C116
0.1uF
R40 10KR40 10K
U10
NC7S04
U10
NC7S04
2 4
53
-
+
U9A
NJM4580E
-
+
U9A
NJM4580E
3
2
1
C118
0.1uF
C118
0.1uF
J8
HEADER2
DNS
J8
HEADER2
DNS
1
2
Y2
12.2880 MHz
Y2
12.2880 MHz
VCC33
4
OUT
3
GND
2
EN
1
+
-
U9B
NJM4580E
+
-
U9B
NJM4580E
6
5
7
84
C115
0.1uF
C115
0.1uF
C102
0.1uF
C102
0.1uF
D4
BAS70H
D4
BAS70H
C105
0.1uF
C105
0.1uF
C104
0.1uF
C104
0.1uF
RN26 150RN26 150
1
2
3
4
8
7
6
5
U7A
NC7WZ125
U7A
NC7WZ125
1
2 6
84
C114
0.1uF
C114
0.1uF
R46
10K
R46
10K
RN29
10K
RN29
10K
1
2
3
4
8
7
6
5
C119
0.1uF
C119
0.1uF
U6
74HC245
U6
74HC245
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
OE
19
DIR
1
B0
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
VCC
20
GND
10
R35
10K
R35
10K
C113
0.1uF
C113
0.1uF
C103
0.1uF
C103
0.1uF
*
*
U12
MT46V8M16P-75
*
*
U12
MT46V8M16P-75
DQ0
2
DQ1
4
DQ2
5
DQ3
7
DQ4
8
DQ5
10
DQ6
11
DQ7
13
DQ8
54
DQ9
56
DQ10
57
DQ11
59
DQ12
60
DQ13
62
DQ14
63
DQ15
65
LDQS
16
UDQS
51
VREF
49
VDD
1
VDD
18
VDD
33
VDDQ
3
VDDQ
9
VDDQ
15
VDDQ
55
VDDQ
61
VSS
34
VSS
48
VSS
66
VSSQ
6
VSSQ
12
VSSQ
52
VSSQ
58
VSSQ
64
A0
29
A1
30
A2
31
A3
32
A4
35
A5
36
A6
37
A7
38
A8
39
A9
40
A10
28
A11
41
A12
42
A13
17
CK
45
CK
46
CS
24
CKE
44
BA0
26
BA1
27
LDM
20
UDM
47
WE
21
CAS
22
RAS
23
RN28 150RN28 150
1
2
3
4
8
7
6
5
C109
0.1uF
C109
0.1uF
J9
HEADER2
DNS
J9
HEADER2
DNS
1
2
J10
HEADER 7X2
J10
HEADER 7X2
2
4
6
8
10
12
14
1
3
5
7
9
11
13
R39 22R39 22
RN30
10K
RN30
10K
1
2
3
4
8
7
6
5
R47
10K
R47
10K
R38
10.0K
R38
10.0K
R44
6.65K
R44
6.65K
U11
XC9536XL
U11
XC9536XL
VCCIO
26
VCC
35
VCC
15
I/O
2
I/O
3
I/O
5
I/O
6
I/O
7
I/O
8
I/O
12
I/O
13
TCK
11
I/O
14
I/O
16
I/O
18
I/O
19
I/O
20
I/O
21
TMS
10
DDR_BA_1
DDR_A_12
DDR_A_11
DDR_A_10
DDR_A_9
DDR_A_8
DDR_A_7
DDR_A_6
DDR_A_5
DDR_A_4
DDR_A_3
DDR_A_2
DDR_A_1
DDR_A_0
DDR_BA_0
DDR_D_15
DDR_D_14
DDR_D_13
DDR_D_12
DDR_D_11
DDR_D_10
DDR_D_9
DDR_D_8
DDR_D_7
DDR_D_6
DDR_D_5
DDR_D_4
DDR_D_3
DDR_D_2
DDR_D_1
DDR_D_0
CPLD_TMS
CPLD_TCK
CPLD_TDO
CPLD_TDI
CPU_D_3
CPU_D_2
CPU_D_1
CPU_D_0
CPU_D_7
CPU_D_6
CPU_D_5
CPU_D_4
B_SP_TBD2
SPD_4
SPD_5
SPD_6
SPD_7
SPD_0
SPD_1
SPD_2
SPD_3
SPANA_IN_P
SPANA_IN_N
SPEN_L
VCC33_ISO_U14
B_SPRES_L
B_SPREN_KY_L
B_SP_TBD1
B_SPEN_AN_L
B_SPREN_SW_L
B_SPREN_LED_L
SPBLANK_L
B_SPBLANK_L
SPREN_KY_L
SPWEN_LED_L
SPRES_L
SPEN_AN_L
SPREN_SW_L
SPEN_L
DDR_D_[15:0]sh.2
DDR_A_[12:0]sh.2
DDR_BA_[1:0]sh.2
DDR_CAS_Lsh.2
DDR_RAS_Lsh.2
DDR_WE_Lsh.2
DDR_CLK_Hsh.2
DDR_CLK_Lsh.2
DDR_CKEsh.2
DDR_VREFsh.2
DDR_DQS_2 sh.2
DDR_DQS_0 sh.2
DSP_RESET_SEL_L sh.1,5
CPU_WAIT_Lsh.1,2,5
SDRAM_CLKsh.1,5
DAC_CLK12_288 sh.4
M1_CLK12_288_IN sh.2
MARA_WR_L sh.2
CPU_WR_BUF_L sh.4
CPU_WR_Lsh.1,5
CPU_D_[7:0]sh.1,2,4,5
CPU_WR_BUF_Lsh.4
BRITEsh.1,4
SPANA_OUT1sh.1
SH_AVCC sh.1
SH_AVCC sh.1
SH_AN0 sh.1
SPRES_L
SPREN_KY_L
SPREN_SW_L
SPEN_AN_L
SPWEN_LED_L
SPBLANKsh.1
RESET_Lsh.1,5
ADTRG_Lsh.1,5
FLRD_L sh.1
EPROM_INST_L sh.1
UART_RD_L sh.1
UART_WR_L sh.1
CPU_WR_BUF_L sh.4
DSP_RESET_L sh.2,5
CPU_A_19 sh.1,5
FLASH_CS_Lsh.1,5
LCD_CS_L sh.1,4,5
SCAN_CS_Lsh.1,5
UART_CS_Lsh.1,5
BOOT_CS_L sh.1,5
CPU_A_21 sh.1,5
CPU_A_20sh.1,5
BOOT_FL_CS_Lsh.1
BOOT_E_CS_Lsh.1
FLWR_L sh.1
LCDEsh.4
CPU_RD_Lsh.1,4,5
BOOT_FL_OE_Lsh.1
SCAN_CS_Lsh.1,5
MARA_CS_L sh.2
MARA_1_CS_L sh.1, 5
TDI
9
TDO
24
I/O
22
I/O
23
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
GND
4
GND
17
GND
25
I/O/GCK1
43
I/O/GCK2
44
I/O/GCK3
1
I/O/GSR
33
I/O/GTS1
36
I/O/GTS2
34
D3
BAS70H
D3
BAS70H
RN23
10K
RN23
10K
1
2
3
4
8
7
6
5
L8
600 OHM @ 100MHz
L8
600 OHM @ 100MHz
C106
0.1uF
C106
0.1uF
C107
0.1uF
C107
0.1uF
12
J7
HEADER 13X2
J7
HEADER 13X2
2
4
6
8
10
12
14
16
18
20
22
24
26
1
3
5
7
9
11
13
15
17
19
21
23
25
C120
0.1uF
C120
0.1uF
R37
3.32K
R37
3.32K
RN25 150RN25 150
1
2
3
4
8
7
6
5
C112
0.1uF
C112
0.1uF
R43
6.65K
R43
6.65K
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