Kurzweil K2000 - Specific Component Test Descriptions (v0.4)

SECTION 4
DIAGSO_4.DOC 12122/92
in the following format: the expected address; the observed address. See
Figure 4.6 for an example.
NOTE: Many figures in this document show values of all zeros. You'll see
non-zero values for the address, expected values, and observed values of all
tests. The expected and observed values themaelves are not significant;
what's important is that a difference between the expected and observed values
indicates a test failure.
Press an~ke~ to continue ..•
Figure 4.6.
Address Failure
4.13.2
ROM Tests
Since data cannot be written to ROM components, tests are done by reading the
data from the ROM components and summing the hexadecimal values of the data.
This sum is compared to a checksum stored in the last two memory addresses of
each component. The two sums must match for the test to pass.
4.13.3
I/O Tests
In an I/O test, a test data pattern is sent from the CPU to the component
being tested. The signal is processed by the component, and returned to the
central processor. If the signal returns to the central processor as
expected, the test is a success. If the observed pattern differs from the
expected pattern, the test fails.
Each of the tests described below will be either a memory test or an I/O test
(or, in some cases, a combination of the two). When performing single passes
of specific tests, the display will indicate the result of the test upon its
completion. In most cases, the result will be Success (Pass), Data Fail, or
Address Fail. Unless otherwise specified, failures will be displayed as
described in the previous paragraphs.
4.14
DESCRIPTIONS OF TESTS
4.14.1
LCD Test
This test has both an I/O stage and a memory stage. It checks the connections
between the LCD and the engine board, as well as the memory of the LCD itself.
The processor writes a test data pattern to the LCD memory, then reads it back
expecting a certain value. If the observed value does not match the expected
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