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Kurzweil K2000 - Interface and Controller Tests (v0.4)

Kurzweil K2000
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SECTION 4
DIAGSO_4.DOC
12/22/92
value,
a
data
failure
is
indicated.
This
could
indicate
a
processor
error,
a
faulty
LCD,
or
a
faulty
connection
from
the
LCD
to
the
engine
board.
4.14.2
Boot
EPROM
Test
This
memory
test
checks
the
integrity
of
the
Engine
software
data
stored
in
the
ROM
chips
located
on
the
engine
board
at
U3
and
U6.
It
reads
the
data
from
each
address
and
compares
it
to
a
checksum
stored
in
the
ROM
chips.
It
also
checks
for
errors
in
the
pin
connections
of
each
of
these
chips.
If
all
checksums
match,
the
test
is
a
success.
If
there
are
checksums
that
do
not
match,
the
display
will
show
either
"Even
Fail"
or
"Odd
Fail."
If
you
see
an
Even
Fail
message,
remove
the
chip
located
at
U3
and
test
it
in
an
EPROM
programmer.
If
the
checksums
match,
the
chip
is
good,
and
a
connection
problem
at
U3
is
indicated.
If
the
checksums
do
not
match,
the
chip
is
improperly
programmed
and
should
be
either
reprogrammed
or
replaced.
Likewise,
if
you
see
an
Odd
Fail
message,
remove
and
test
the
chip
from
location
U6.
NOTE:
The
sockets
at
U3
and
U6
are
labeled
"SETUP"
on
the
engine
board.
Even
so,
the
chips
installed
in
these
sockets
are
the
Engine
software
EPROMs.
This
discrepancy
is
due
to
a
design
change
that
was
made
after
the
engine
board
was
finalized
and
printed.
For
Engine
software
Version
1.0,
the
SETUP
sockets
contain
the
Engine
software,
and
locations
U2
and
US
are
unused.
Nevertheless,
the
Boot
EPROM
test
checks
the
Engine
software
EPROMs.
4.14.3
setup
EPROM
Test
Similar
to
the
Boot
EPROM
test,
this
is
intended
to
check
the
data
and
pin
connections
of
the
ROM
chips
located
at
U2
and
uS
on
the
engine
board.
For
Engine
software
Version
1.0,
these
locations
are
unused,
and
the
test
will
fail.
This
does
not
indicate
a
malfunction.
4.14.4
PSRAM
Test
This
is
a
memory
test
of
the
pseudo-static
RAM
chips
located
at
U07
and
U08
on
the
engine
board.
The
results
will
be
either
Success,
Data
Failure,
or
Address
Failure.
If
this
test
fails,
the
RAM
chips
should
be
replaced.
4.14.5
I/O
Port
Test
In
this
test,
the
integrity
of
data
transfer
within
the
CPU
(location
U9)
is
tested.
This
is
done
by
writing
a
test
data
pattern
from
the
low
bit
addresses
of
the
CPU
to
the
high
bit
addresses.
The
high
bits
then
read
the
pattern
and
compare
it
to
the
original.
If
the
patterns
match,
the
test
is
a
success.
If
the
test
fails,
the
CPU
may
be
bad,
but
it
is
more
likely
that
there
is
a
problem
with
the
I/O
bus.
4.14.6
Interrupt
Test
Also
an
I/O
test,
the
Interrupt
Test
checks
the
connection
between
the
IRQO
(interrupt
request)
pin
and
the
floppy
disk
controller
in
the
CPU. A
successful
Interrupt
test
indicates
that
interrupt
requests
from
the
floppy
disk
controller
are
being
received
by
the
CPU's
IRQO
pin.
Failure
of
this
test
indicates
a
defective
connection
between
the
CPU's
IRQO
pin
and
floppy
disk
controller,
and
could
identify
the
cause
of
malfunctions
in
the
floppy
disk
drive.
16

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