LabJack UE9 - Page 20

Timer Modes
0
16-bit PWM output
1
8-bit PWM output
2
Period input (32-bit, rising edges)
3
Period input (32-bit, falling edges)
4
Duty cycle input
5
Firmware counter input
6
Firmware counter input (with debounce)
7
Frequency output
8
Quadrature input
9
Timer stop input (odd timers only)
10
System timer low read
11
System timer hight read
12
Period input (16-bit, rising edges)
13
Period input (16-bit, falling edges)
Table 2.10-1. UE9 Timer Modes
TimerClockBase
0
750 kHz
1
48 MHz (System)
Table 2.10-2. UE9 Timer Clock Options
All timers use the same timer clock (which affects modes 0, 1, 2, 3, 4, 7, 12, and 13). The timer clock is determined by dividing the
base clock by the clock divisor. The divisor has a range of 0-255, where 0 corresponds to a division of 256. There are 2 choices
for the timer base clock.
The low level TimerCounter function has a bit called UpdateConfig that must be set to change the timer clock, timer modes, or
number of timers/counters enabled. When this bit is set, all timers and counters are re-initialized. The LabJackUD driver
automatically sets this bit if any write requests are executed related to mode, enabling/disabling, or clock configuration.
The low level TimerCounter function has UpdateReset bits for each timer that must be set to change the timer value. The
LabJackUD driver automatically sets the appropriate bit when a value write is executed.
The low level TimerCounter function has Reset bits for each counter that must be set to reset the counter to zero. The LabJackUD
automatically sets the appropriate bit when a reset request is executed.
2.10.1 - Timer Mode Descriptions
2.10.1.1 - PWM Output (16-Bit, Mode 0)
Outputs a pulse width modulated rectangular wave output. Value passed should be 0-65535, and determines what portion of the
total time is spent low (out of 65536 total increments). That means the duty cycle can be varied from 100% (0 out of 65536 are low)
to 0.0015% (65535 out of 65536 are low).
The overall frequency of the PWM output is the clock frequency specified by TimerClockBase/TimerClockDivisor divided by 2
16
.
The following table shows the range of available PWM frequencies based on timer clock settings.
PWM16 Frequency
Ranges
TimerClockBase
Divisor=1
Divisor=256
0
750 kHz
11.44
0.04
750000
1
48 MHz (System)
732.42
2.86
48000000
Table 2.10.1.1-1. 16-bit PWM Frequency Ranges
The same clock applies to all timers, so all 16-bit PWM channels will have the same frequency and will have their falling edges at
the same time.
PWM output starts by setting the digital line to output-low for the specified amount of time. The output does not necessarily start
instantly, but rather waits for the internal clock to roll. For example, if the PWM frequency is 100 Hz, that means the period is 10
milliseconds, and thus after the command is received by the device it could be anywhere from 0 to 10 milliseconds before the start
of the PWM output.
If a duty cycle of 0.0% (totally off) is required, consider using a simple inverter IC such as the CD74ACT540E from TI.
2.10.1.2 - PWM Output (8-Bit, Mode 1)
Outputs a pulse width modulated rectangular wave output. Value passed should be 0-65535, and determines what portion of the
total time is spent low (out of 65536 total increments). The lower byte is actually ignored since this is 8-bit PWM. That means the
duty cycle can be varied from 100% (0 out of 65536 are low) to 0.4% (65280 out of 65536 are low).
The overall frequency of the PWM output is the clock frequency specified by TimerClockBase/TimerClockDivisor divided by 2
8
.
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