Lattice Semiconductor CrossLink-NX - Acronyms in this Document

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CrossLink-NX Object Counting Using VGG Quick Start Guide

Application Note

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4 FPGA-AN-02024-1.0

Acronyms in This Document

A list of acronyms used in this document.

Acronym

Definition

FPGA

Field-Programmable Gate Array

VIP

Video Interface Platform

Main Page

Table of Contents3
Acronyms in this Document4
Introduction5
Design Process Overview5
Figure 1.1. Lattice EVDK with Microsd Card Adapter Board5
Figure 1.2. Lattice Machine Learning Design Flow6
Machine Training and Creating Frozen File7
Verifying Tensorflow and Tool Environment7
Preparing the Dataset7
Figure 2.1. Tensorflow Installation Check7
Figure 2.2. Dataset Image Size Check7
Training the Machine8
Figure 2.3. Dataset Folder Path Check8
Figure 2.4. Dataset List, Image, and Label Data Path8
Figure 2.5. Create a Label File8
Figure 2.6. Execute the Script9
Figure 2.7. Tensorboard - Generated Link9
Figure 2.8. Training Status9
Figure 2.9. Image Menu10
Figure 2.10. Checkpoint Data Files at Log Folder10
Generating Frozen (*.Pb) File11
Figure 2.11. Create *.Pbtxt File11
Figure 2.12. Check Frozen File11
Generating the Binary File12
Programming the Bitstream and Binary Files to VIP Board and SD Card12
Technical Support Assistance13
Revision History14

Lattice Semiconductor CrossLink-NX - Acronyms in this Document

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