CrossLink-NX Object Counting Using VGG Quick Start Guide
Application Note
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-AN-02024-1.0 5
1. Introduction
This document provides a quick guide on how to train a machine and create a frozen file for the Lattice Machine
Learning development using the Lattice’s Embedded Vision Development Kit. It assumes that you are familiar with the
basic Lattice FPGA design flow and mainly focuses on the Machine Learning part of the overall development process.
For detailed instructions of the design flow described in this document, refer to the CrossLink-NX Object Counting
Using VGG CNN Accelerator IP (FPGA-RD-02200).
Figure 1.1. Lattice EVDK with MicroSD Card Adapter Board
1.1. Design Process Overview
The design process involves the following steps:
1. Setting up the basic environment
2. Preparing the dataset
3. Training the machine
4. Creating the frozen file (*.pb)
5. Creating the binary file with Lattice sensAI™ 3.0 program
6. Programming the binary and bitstream files to VIP board and SD card
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