Lattice Semiconductor ECP5 - Design Process Overview; Figure 1.2. Lattice Machine Learning Design Flow

15 pages

To Next Page

To Previous Page

ECP5 Face Identification Quick Start Guide

Application Note

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

6 FPGA-AN-02010-1.0

1.1. Design Process Overview

The design process involves the following steps:

 Setting up the basic environment

 Preparing the dataset

 Training the machine

 Creating the frozen file (*.pb)

 Creating the binary file with Lattice sensAI™ 2.1 program

 Programming the binary and bitstream files to VIP board and SD card

Figure 1.2. Lattice Machine Learning Design Flow

Main Page

Table of Contents3
Acronyms in this Document4
Introduction5
Figure 1.1. Lattice EVDK with Microsd Card Adapter Board5
Design Process Overview6
Figure 1.2. Lattice Machine Learning Design Flow6
Machine Training and Creating Frozen File7
Caffe Installation7
Preparing the Dataset7
Training the Machine with Caffe8
Figure 2.1. Default Content of the Train Folder8
Figure 2.2. Machine Training Contents8
Figure 2.3. Update Proto File for Dataset Label File Name8
Figure 2.4. Last Fully-Connected Layer Output Number Setting9
Figure 2.5. Train.sh Parameter Setting Example9
Figure 2.6. Executing Train.sh Script Command9
Figure 2.7. Training Status Example10
Figure 2.8. Machine Training Output File10
Training the Machine with Tensorflow11
Generating the Frozen (*Pb) File11
Figure 2.9. Machine Training Output File11
Figure 2.10. Tensorboard - Launch11
Figure 2.11. *Pb File Generation from Checkpoint11
Generating the Binary File12
Programming the Bitstream and Binary Files to VIP Board and SD Card12
Technical Support Assistance13
Revision History14

Lattice Semiconductor ECP5 - Design Process Overview; Figure 1.2. Lattice Machine Learning Design Flow

Table of Contents

Other manuals for Lattice Semiconductor ECP5

Related product manuals