has higher priority than IR2,
it
won't be acknowledged
until the
IR2
routine
is
finished (via
EOI).
This
is
because
priorities are only resolved upon an interrupt request or
an interrupt acknowledge sequence.
If a higher priority
request occurs during the IR2 routine, then priorities are
resolved and the highest will be acknowledged.
When completing a service routine in which the set
priority command
is
used, the correct
EOI
must be
issued. The non·specific
EOI
command shouldn't be
used in the same routine as a set
priority
command.
This
is
because the non-specific
EOI
command resets
the highest
ISR
bit. which, when using the set priority
command, is not always the most recent routine in ser-
vice. The automatic
EOI
mode, on the other
ha"nd.
can be
used with the set priority command. This is because
it
automatically performs a non·specific
EOI
before the
set priority command can be issued. The specific
EOI
command
is
the best bet in most cases when using the
set priority command within a routine.
By
resetting the
specific ISR
bit
of a routine being completed, confusion
is
eliminated.
Rotate on $pecltlc
EOI
Command
The rotate on specific
EOI
command is literally a com·
bination
of
the set priority command and the specific
EOI
command. Like·the set priority command, a speci·
fied
IR
level
is
assigned lowest priority. Like the specific
EOI
command, a specified level will be reset in the ISR.
Thus the rotate on specific
EOI
command accomplishes
both tasks in only one command.
It
it
is
not necessary
to
change
IR
priorities prior
to
the
end of an interrupt routine, then
this
command is advan.
tageous. For
an
EOI
command must be executed any.
way (unless in the automatic
EOI
mode), so why not do
both at the same time?
44
Interrupt Masking
Disabling or enabling interrupts can be done by other
means than just controlling the microprocessor's inter·
rupt request pin. The 8259A has
an
IMR (Interrupt Mask
Register) which enhances interrupt control capabilities.
Rather than all interrupts being disabled or enabled at
the same time, the IMR allows individual
IR
masking.
The IMR is an a·bit register.
bits
0-7
directly correspond
to
IRO-IR7. Any IR input can
be
masked by writing
to
the
If'
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of
a lower priority than the routine in service. Or, in other
words, allow lower priority devices to generate inter·
rupts. However, in the fully nested mode.
alliR
levels
01
priority below the routine in service are inhibited
So
what can
be
done
to
enable them?
Well, one method could be using
an
EOI
command
before the actual completion of a routine
In
service. But
beware, doing this may cause an "over nesting" prob·
lem, similar
to
in the automatic
EOI
mode.
In
addition.
resetting an
ISR
bit
is
irreversible by software control.
so lower priority
IR
levels could only be later disabled
by
setting the IMR.
A much better solution is the special mask mode. Work-
ing in conjunction with the
1M
A,
the special mask mode
enables interrupts from all levels except the level in ser·
vice. This is done by masking the level that is in service
and then issuing the special mask mode command.
Once the special mask mode is set, it remains
in
effect
until
reset.
Figure
15
shows
.how
to
enable lower priority interrupts
by using the Special Mask Mode (SMM). Assume that
IRO
has highest priority when the
maIO
program IS inter·
rupted by IR4.
In
the
IR4
service routine
an
enable inter·
rupt
instruction
is executed. This only allows hlgner
priority interrupt requests to interrupt
IR4
in the normal
fully nested mode Further in the
IR4
routine. bit 4 of the
IMA is masked and the special mask mode is entered.
Priority operation is no longer in the fully nested mode.
All interrupt levels are er,abled except for
IR4.
To
leave
the special mask mode, the sequence is executed
In
reverse.
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