Lexicon MPX-1 User Manual

ACCESSING I/O PORTS ON THE BUS
All of the "I/O Ports" local to the MPX-l are "memory mapped". This means
they are decoded in the memory address space rather than in the I/O space. This
leaves all 256 I/O addresses free. Any input or output cycle performed by the
CPU will cause a corresponding cycle to be executed on the S-lOO Bus. Since the
lower 8 bits of the DMA Address pass through from the actual lower 8 address
bits from the CPU, the port address specified in the I/O instruction will be the
one accessed on the bus.
The high order 8 bits of the I/O access will come from the DMA address
register as in a memory reference. This allows the port aduress to be
"mirrored" in A8-lS as early S-lOO (8080) processors did, or thit> byte may be
loaded with different data to emulate Z-80 I/O modes (the 2-8U passes the
accumulator contents on A8-l5). This also allows the MPX-1 to emulate the
current generation of 16 bit processors such as the CPU 8085/88, CPU 86/87 and
the CPU 68K, which can put out 16 bit I/O addresses.
If an input instruction is executed, then an input cycle will be performed
on the S-lOO Bus. If an output instruction is executed, then an output cycle
will be performed on the bus.
GE'ITING THE HPX-l's ATTENTION
In any system it will be necessary for the main CPU in the sydcem to get
the attention of the MPX-l. This can be for initial start-up of the MPX-l, or
to "interrupt" its current task to be given another. This is done through a
mechanism called the ATTN port. This port is on the S-100 Bus and its address
is selec ted by swi tch S1. When the system CPU executes an output to the ATTN
port, a RST 7.5 will be generated to the on-board 8085. Note that no data is
accepted by the MPX-l. .~
GET'l'ING THE MAIN SYSTEM CPIrS ATTENTION
The MPX-1 may need to get the attention of the system CPU to tell it that a
task is complete, a buffer is nearing full, or many other reasons. The MPX-1
may
signal the main CPU by causing an interrupt on the bus. This interrupt may
occur on the INT*, NMI* or any of the vectored interrupt lines. A hardware
jumper is used to select which of the ten possible lines are used.
Two methods of causing this interrupt are available, again selected by a
jumper. The first type uses the Serial Output Data (SOD) line from the 8085 to
cause the interrupt. The state of this line is set and reSet by the Set Inter-
rupt Mask (SIM) instruction. The state of the interrupt request must be reset
in software.
The second method uses a one bit latch that is set by performing a read
from address 8002 (set Interrupt Latch in the address map above). This latch is
automatically reset by the occurrence of an interrupt acknowledge cycle.
Note that if one of the vectored interrupt lines is selected to cause the
system interrupt, the corresponding interrupt input to the 8259A should be
masked, unless you want the MPX-l to interrupt itself.
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Lexicon MPX-1 Specifications

General

Brand	Lexicon
Model	MPX-1
Category	Recording Equipment
Language	English