MPX 500 Service Manual
6-2
The configuration resistors R115-R122 on system data bus are used to program the Lexichip3 operating
mode. Upon the rising edge of RESET/, various Lexichip3 mode bits are set which determines the system
operating parameters. If any chip on the Z80 data bus erroneously drives the data bus during RESET/, the
Lexichip3 will come up in the wrong mode and the Z80 will not function properly. Therefore, during
RESET/, all the relevant chip enables must be pulled high and the Z80 must be fed clocks to allow the
resistors to work as designed. Proper initialization of the system is dependent on the static state of the data
bus on power up which is provided by R115-122 and on the default state of other lines governed by R10,
R17, R23-24, R80-81, R54-56, R95, R76, R114. Be sure to check these and clocks if the system will not
come up.
The Z80 (U13) handles all basic system control and user interface I/O operation. Normally, the Z80 clock
ZCLK is derived from the Lexichip3 M_ZCLK pin, via GAL U20 (sheet 5). However, when RESET/ is
asserted, before the Lexichip3 is functioning, the GAL feeds ZCLK from the 12.288MHz crystal oscillator.
The Lexichip3 master clock (CLK_IN, pin 75), is driven by 256FS48, from the 12.288MHz crystal oscillator
(sheet 5). All the system software and programs are stored in 256Kx8 EPROM (U9). The Z80’s memory is
a 32Kx8 SRAM (U2). User programs are stored in a 4kx8 EEPROM (U5). The EEPROM clock is driven by
the Lexichip3 under program control. The serial data line (EEPROM_DATA) is bi-directional. R22 prevents
excessive current in either the EEPROM or the Lexichip3 during power-up, when both chips might drive the
line. The audio memory for the Lexichip3 is provided by 1Mx4 DRAM (U6). Note that all address decoding
(RAM_EN/, ROM_EN/, etc.) is done within the Lexichip3. That is the primary reason the Z80 cannot
function if the Lexichip3 is improperly initialized at the rising edge of RESET/.
Sheet 4 (ENCODERS)
This sheet shows the front panel PROGRAM EDIT encoders and their associated circuits.
Four-bit gray-code encoders SW1-SW4 are multiplexed two at a time onto a shared 8-bit bus, ENC [7-0],
which is readable by software. Pull-up resistors R124-R131 default the bus to logic high.
Diodes D12-D15 (Program Edit 4 encoder), D16-D19 (Program Edit 3 encoder), D20-D23 (Program Edit 2
encoder), D24-D27 (Program Edit 1 encoder) are used to isolate the output of the unselected encoder pair
during the reading of the selected encoder pair. An encoder is selected when its C pin is set low, which
allows the encoder to assert its current position onto the ENC bus via the corresponding group of diodes.
The C pin is controlled via Lexichip3 (sheet 3) PIO bits. In addition to the encoders, the closure of the
individual front panel switches associated with D5, D6, D28, D29, D7, D8 and D9 can be read when
SWITCH_SELECT/ (sheet 6, A5) is asserted. Software selects which set of signals is placed on the ENC
bus by asserting ADJ12_SELECT/, ADJ34_SELECT/, or SWITCH_SELECT/. The state of the ENC bus is
then read via the 74HC541 (U23).
Sheet 5 (MIDI, DIGITAL AUDIO OUT)
This sheet shows the Clock generation, MIDI I/O and S/PDIF I/O and their associated circuits.
At the center of the sheet are the crystal oscillators, which are the basis for the two sample rate clocks (44.1
kHz and 48 kHz). These clocks, 256FS441 and 256FS48M, plus 256FSPLL, from the digital audio
receiver, are fed to 74HC153 (U15) where they are software selected via CLK_SEL0 and CLK_SEL1. A
GAL16V8R-25 (U10) provides various clocks and control signals including ZRST/ to the Z80. The
Lexichip3 is clocked by 256FS48, and is set to execute 255 instructions out of a possible 256. This means
that it will execute DSP operations properly at 48 kHz + ca. 0.4% (1/256).
The MPX500 MIDI interface complies with the MIDI specification. It incorporates 5-pin female DIN
connectors for input, thru and out (J2 and J3). J3 is shared for thu and out, according to how the Lexichip3
is programmed. MIDI INPUT is opto-coupled for ground isolation through U1 to the MIDI UART within the
Lexichip3 (sheet 3). The MIDI OUTPUT signal is generated by the Lexichip3 (sheet 3) and is fed to current
loop driver Q1 and out J3. FB1-2 and J2-3 shields connection to ground are to reduce RFI.
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