LG 42LV3500 - System Diagrams, PCB Layouts, and Interconnections; Block Diagram and Exploded View

- 15 -
LGE Internal Use OnlyCopyright ©2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BLOCK DIAGRAM
NAND
Flash ( 8Gb)
Audio
AMP
PCMCIA
Tuner_CVBS
USB
COM P1
A/V1 SCART
RS-232C PC- RGB PC- AUDI O SPDI F
SYSTEM
DDR3 X 16 X 2
(2Gb)
51P
HDMI 1 HDMI 2
HDMI 3
H/ P
SYSTEM EEPROM X 1
(1Mb)
TUNER
(T/ C)
41P
SPI
Flash ( 2M b )
SYSTEM
DDR3 X 16 X 1
(1Gb)
Tuner_SI F
SCL/ SDA
CI_TS_DATA[7:0]/CLK/Valid/Sync
CI _DATA[ 7:0]
CI _ ADDR[ 14 : 0 ]
FE_TS_DATA[0]/CLK/Valid/Sync
USB_DM/ DP
HP_OUT
DSUB_RGB/ HVsync
DDC_SDA/ UART_TX
PC_ Au d i o I N
SPDI F_OUT
Debug _TX/ RX
SC_CVBS/ RGB/ LR_ I N
SC_VI DEO/ LR_OUT
AV_CVBS/ LR_I N
COMP_ YPb Pr / LR_ I N
HDMI _TMDS/ HPD/ CEC
HDMI _TMDS/ HPD/ CEC HDMI _TMDS/ HPD/ CEC
I2S_I/F
SCL/ SDA
30P
Side
Rear
DATA
Video
Audio
DATA
Video
Audio
Su b Mi com
(NEC)
HDCP EEPROM X 1
(8Kb)
For FRC
SPI
Flash ( 8M b )
SCL/ SDA
SCL/ SDA
LGE101 (S7R) LGE107 (S7+URSA)