LG 42LV3500 - Block Diagram View

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Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Block diagram
NAND
Flash(1Gb)
Audio
AMP
PCMCIA
Tuner_CVBS
USB
COMP1
A/V1
SCART
RS-232C
PC-RGB
PC-AUDIO
SPDIF
SYSTEM
DDR3 X 16 X2
(1Gb)
51P
HDMI1
HDMI2
HDMI3
H/P
SYSTEM EEPROM X 1
(1Mb)
TUNER
(T/C)
41P
SPI
Flash(2Mb)
FRC
DDR3 X 16 X 1
(1Gb X 1)
Tuner_SIF
SCL/SDA
CI_TS_DATA[7:0]/CLK/Valid/Sync
CI_DATA[7:0]
CI_ADDR[14:0]
FE_TS_DATA[0]/CLK/Valid/Sync
USB_DM/DP
HP_OUT
DSUB_RGB/ HVsync
DDC_SDA/UART_TX
PC_ Audio IN
SPDIF_OUT
Debug _TX/RX
SC_CVBS/RGB/LR_IN
SC_VIDEO/LR_OUT
AV_CVBS/LR_IN
COMP_ YPbPr/ LR_IN
HDMI_TMDS/HPD/CEC
HDMI_TMDS/HPD/CEC
HDMI_TMDS/HPD/CEC
I2S_I/F
SCL/SDA
30P
Side
Rear
DATA
Video
Audio
Sub Micom
(NEC)
HDCP EEPROM X 1
(8Kb)
Only for FRC or 3D Model
SPI
Flash(8Mb)
SCL/SDA
SCL/SDA
LGE101 (S7)
LGE107 (S7+FRC)