LG 42PG20 - Page 80

80
Plasma Fall 2008 42PG20
VS VS is input at P1 pin 1 and supplied to the FETs.
Input Voltages from the Y SUS Board
Input Voltages from the Y SUS Board
Z
Z
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SUS PWB Understanding
SUS PWB Understanding
The Z
The Z
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SUS Board in this model is only a small vertical board with outp
SUS Board in this model is only a small vertical board with outp
ut FETs.
ut FETs.
Drive waveforms are generated on the Y
Drive waveforms are generated on the Y
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SUS PWB.
SUS PWB.
Z Drive Signals to Power FET’s
Input Signals from the Y SUS Board
Input Signals from the Y SUS Board