LG 55EA8800 - Page 55

H13 Block diagram
DIF
TS (P)
System
D
Global Baseband
H13A H13D
Video Decoder
Multi
-
STD
UART 3
TS(P) TS(P)
GBB AFE
1ch@30MHz
DVB-CI/CI+
TS(S)
GPU Rogue Han
USB2.0x3
TS(S)
SDRAM
(MCP)
Tuner
D
emux
Audio DSP
Multi-STD
Audio Decoder
LX4 HiFi EP
SIF
Global
Baseband
V/Q, DVB-T/C ISDB-T
AAD
(THAT)
Mux
I2S(External)
Multi
STD
HD Decoder
(Boda950)
Audio
2D GFX
JPG/PNG Decoder
JPG Encoder
UART
x
3
EMAC
SCI
SPIx2
I2Cx10
PHY
1ch@30MHz
w/ PLL
BTSC AFE
10b@18.432MHz
w/ PLL
Video Encoder
1080p@30fps
GPIOx136
Audio L/R(4-ch)
SCART out
SW
Audio DAC (48KHz)
Line Out
TrustZone
CPU
ARMCA9 Core
Dual 1.2GHz
Sound DSP
Clear Voice II
Perceptual
Volume Control
I2S
I2S(HPD)
CPU
64KB SRAM
48KB ROM
OTP
I2Cx10
eMMC
DMAC(8ch)
Timer
WDT
1ch L/R
Audio-ADC
24b@48KHz
USB3.0 x1
Secure Engine
Audio DAC
(48KHz )
I2S
I2S
SW
CVBS(3ch)
CVBS
Encoder
32KBI$
32KBD$
1MB L2 $
Slim SPK
DivX
Bluetooth
Digital AMP
I2S(HPD)
SPDIF
UART
OTP
Timer
SRAM 16KB
Digital
Audio
Output
CVBS DAC
5x1ch (1ch)
Component(2ch)
CVBS AFE(2-ch)
12b@54MHz
CVBS-Out
Mux
10x3ch
DE
Encoder
LVDS
Tx
e
Mux
R
e
rlacer
b
Scaler
D
C
R
SWSW
3ch Video
AFE
10b@148.5MHz
LVDS
Rx
CVD
Y/C
CVBS
BE
D
R
C
R
E
E
1
S
D
D
o
rmatter
O
N
MCU
Capture
Block
(3CH)
Mux
/
EPI/LVDS Combo
(120Hz)
MCU
HDMI-Rx 1.4
(1-port PHY)
DDR3 Controller
Audio PLL
w/ DCO
Sourc
e
TN
De-int
e
Main/Su
b
H3
V
C
w/ LLPLL
I2Cx1
H3
DDR3 Controller
SPLL
DDR
DPLL
DDR
F
R
S
R
P
E
O
S
LE
Output f
o
TC
O
(3CH)
I2Cx1
HDMI
(1-Link)
HDMI
Vx1
/
CPLL
DCO
x2
GPIOIx16
3D, ARC, 4kx2k
DDR3 PHY DDR3 PHY
DDR
PLL
DDR
PLL
16
16
16
16
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