THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
C10103
2.2uF
10V
+2.5V_FPGA
+2.5V_FPGA
TXBCLKP
R10101
4.7K
OPT
R10102
10K
+2.5V_FPGA
C10104
2.2uF
10V
+2.5V_FPGA
TXBCLKN
+2.5V_FPGA
+2.5V_FPGA
TXACLKP
TXACLKN
C10109
0.47uF
25V
C10111
0.47uF
25V
C10113
0.47uF
25V
C10114
0.47uF
25V
+1.2V_FPGA
+1.2V_FPGA
TXB1N
TXB1P
TXB2P
TXB2N
TXB3N
TXB3P
TXB4N
TXB4P
TXA0N
TXA0P
TXA1N
TXA1P
TXA2P
TXA2N
TXA3P
TXA3N
TXA4N
TXA4P
C10101
10uF
16V
C10115
10uF
16V
OPT
C10106
10uF
16V
C10105
10uF
16V
C10116
10uF
16V
OPT
C10117
10uF
16V
OPT
TXB0P
TXB0N
/RESET2V5
Q10101
2SC3052
E
B
C
R10108
4.7K
Q10102
2SC3052
E
B
C
+2.5V_FPGA
R10105
10K
R10111
10K
/FPGA_RESET
R10112
10K
+3.3V_NORMAL
/RESET2V5
FPGA_LINK4A_TXCLKIN_P
FPGA_LINK4A_TXCLKIN_N
FPGA_LINK4A_TXIN2_P
FPGA_LINK4A_TXIN2_N
FPGA_LINK5A_TXCLKIN_P
FPGA_LINK5A_TXCLKIN_N
LINK4A_LOCK_N
LINK3A_LOCK_N
FPGA_DEBUG_0
FPGA_DEBUG_3
FPGA_DEBUG_3
FPGA_DEBUG_2
FPGA_DEBUG_1
FPGA_DEBUG_0
C10102
4.7uF
10V
C10107
4.7uF
10V
C10108
4.7uF
10V
C10110
4.7uF
10V
C10112
4.7uF
10V
R10109
33
P10104
12507WS-08L
1
2
3
4
5
6
7
8
9
OPTIC_FPGA_RESET
C10118
0.1uF
16V
R10106
4.7K
SW10101
JTP-1127WEM
1 2
43
R10107
0
/FPGA_RESET
C10119
0.1uF
16V
R10110
0
OPT
IC10102
KIA7029AF
2
G
3
O
1
I
R10103
330
R10104
1K
+3.3V_NORMAL
IC10101
XC6SLX16-3CSG324I
IO_L54N_M3A11_3
D3
IO_L54P_M3RESET_3
E4
IO_L50P_M3WE_3
E3
IO_L55P_M3A13_3
F6
IO_L55N_M3A14_3
F5
IO_L51P_M3A10_3
F4
IO_L51N_M3A4_3
F3
IO_L53N_M3A12_3
G6
IO_L53P_M3CKE_3
H7
IO_L49P_M3A7_3
H6
IO_L49N_M3A2_3
H5
IO_L44P_GCLK21_M3A5_3
H4
IO_L44N_GCLK20_M3A6_3
H3
IO_L47P_M3A0_3
J7
IO_L47N_M3A1_3
J6
IO_L45N_M3ODT_3
K6
IO_L40P_M3DQ6_3
J3
IO_L42N_GCLK24_M3LDM_3
K3
IO_L42P_GCLK25_TRDY2_M3UDM_3
K4
IO_L43N_GCLK22_IRDY2_M3CASN_3
K5
IO_L43P_GCLK23_M3RASN_3
L5
IO_L45P_M3A3_3
L7
IO_L31P_3
L6
IO_L39P_M3LDQS_3
L4
IO_L83P_3
C2
IO_L83N_VREF_3
C1
IO_L52P_M3A8_3
D2
IO_L52N_M3A9_3
D1
IO_L50N_M3BA2_3
E1
IO_L48P_M3BA0_3
F2
IO_L48N_M3BA1_3
F1
IO_L46N_M3CLKN_3
G1
IO_L46P_M3CLK_3
G3
IO_L41N_GCLK26_M3DQ5_3
H1
IO_L41P_GCLK27_M3DQ4_3
H2
IO_L40N_M3DQ7_3
J1
IO_L38P_M3DQ2_3
K2
IO_L38N_M3DQ3_3
K1
IO_L37N_M3DQ1_3
L1
IO_L37P_M3DQ0_3
L2
IO_L36N_M3DQ9_3
M1
IO_L35P_M3DQ10_3
N2
IO_L35N_M3DQ11_3
N1
IO_L1N_VREF_3
N3
IO_L34N_M3UDQSN_3
P1
IO_L34P_M3UDQS_3
P2
IO_L2N_3
P3
IO_L33N_M3DQ13_3
T1
IO_L33P_M3DQ12_3
T2
IO_L32N_M3DQ15_3
U1
IO_L32P_M3DQ14_3
U2
IO_L36P_M3DQ8_3
M3
IO_L2P_3
P4
IO_L1P_3
N4
IO_L31N_VREF_3
M5
IO_L39N_M3LDQSN_3
L3
VCCO_3_1
E2
VCCO_3_2
G4
VCCO_3_3
J2
VCCO_3_4
J5
VCCO_3_5
M4
VCCO_3_6
R2
IC10101
XC6SLX16-3CSG324I
TCK
A17
TDI
D15
TMS
B18
TDO
D16
SUSPEND
R16
CMPCS_B_2
P13
DONE_2
V17
PROGRAM_B_2
V2
GND_1
A1
GND_2
A18
GND_4
B13
GND_3
B7
GND_6
C16
GND_5
C3
GND_8
D10
GND_7
D5
GND_9
E15
GND_12
G12
GND_13
G17
GND_10
G2
GND_11
G5
GND_15
H10
GND_14
H8
GND_18
J11
GND_19
J15
GND_16
J4
GND_17
J9
GND_21
K10
GND_20
K8
GND_23
L11
GND_22
L9
VCCAUX_1
B1
VCCAUX_2
B17
VCCAUX_5
E14
VCCAUX_3
E5
VCCAUX_4
E9
VCCAUX_6
G10
VCCAUX_7
J12
VCCAUX_8
K7
VCCAUX_9
M9
VCCAUX_11
P10
VCCAUX_12
P14
VCCAUX_10
P5
VCCINT_1
G7
VCCINT_3
H11
VCCINT_2
H9
VCCINT_5
J10
VCCINT_4
J8
VCCINT_7
K11
VCCINT_6
K9
VCCINT_9
L10
VCCINT_8
L8
VCCINT_11
M12
VCCINT_10
M7
GND_26
M17
GND_24
M2
GND_25
M6
GND_27
N13
GND_28
R1
GND_31
R14
GND_32
R18
GND_29
R4
GND_30
R9
GND_33
T16
GND_35
U12
GND_34
U6
GND_36
V1
GND_37
V18
IC10101
XC6SLX16-3CSG324I
IO_L9P_0
E7
IO_L9N_0
E8
IO_L7P_0
F7
IO_L7N_0
E6
IO_L32P_0
G8
IO_L32N_0
F8
IO_L40P_0
G11
IO_L40N_0
F10
IO_L42P_0
F11
IO_L42N_0
E11
IO_L47P_0
D12
IO_L47N_0
C12
IO_L50P_0
C13
IO_L50N_0
A13
IO_L51P_0
F12
IO_L51N_0
E12
IO_L5P_2
U15
IO_L5N_2
V15
IO_L19P_2
T12
IO_L19N_2
V12
IO_L20P_2
N10
IO_L20N_2
P11
IO_L22P_2
M10
IO_L22N_2
N9
IO_L15P_2
M11
IO_L15N_2
N11
IO_L44P_2
N7
IO_L44N_2
P8
IO_L40P_2
M8
IO_L40N_2
N8
IO_L47P_2
N6
IO_L47N_2
P7
Decouplingcapacitors forVCCINT
XILINX JTAG HDR FOR CONFIG OR CHIPSCOPE
Decouplingcapacitors forVCCO Bank3
Decouplingcapacitors forVCCAUX
FPGA Reset Level Shifter (3.3V to 2.5V)
LVDS Signals from 3D Depth IC to FPGA
FPGA Bank_3 :
2.5V Power Rail should be applied.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
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