THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R10204
4.7K
+2.5V_FPGA
+2.5V_FPGA
+2.5V_FPGA
C10207
0.47uF
25V
C10205
0.47uF
25V
C10206
0.47uF
25V
FPGA_SPI_DO
C10203
10uF
16V
C10208
10uF
16V
OPT
+2.5V_FPGA
+2.5V_FPGA
/RESET2V5
R10216
0
OPT
+2.5V_FPGA
L10203
BLM18PG121SN1D
+2.5V_NORMAL
+3.3V_FPGA
+3.3V_NORMAL
L10204
BLM18PG121SN1D
R1020922
R10205
4.7K
R10214
4.7K
OPT
R10206
4.7K
R10215
4.7K
OPT
FPGA_SPI_DI
FPGA_SPI_CLK
FPGA_SPI_CZ
FPGA_LINK3A_TXIN4_P
FPGA_LINK3A_TXIN3_P
FPGA_LINK3A_TXIN1_N
FPGA_LINK3A_TXIN1_P
FPGA_LINK3A_TXIN0_N
FPGA_LINK3A_TXIN0_P
FPGA_LINK3A_TXIN2_P
FPGA_LINK3A_TXCLKIN_N
FPGA_LINK3A_TXIN3_N
FPGA_LINK3A_TXIN4_N
FPGA_LINK3A_TXCLKIN_P
FPGA_LINK4A_TXIN4_N
FPGA_LINK4A_TXIN4_P
FPGA_LINK5A_TXIN1_N
FPGA_LINK4A_TXIN3_P
FPGA_LINK4A_TXIN1_N
FPGA_LINK4A_TXIN1_P
FPGA_LINK4A_TXIN0_N
FPGA_LINK4A_TXIN0_P
FPGA_LINK3A_TXIN2_N
FPGA_LINK5A_TXIN1_P
FPGA_LINK4A_TXIN3_N
FPGA_LINK5A_TXIN4_N
FPGA_LINK5A_TXIN3_N
FPGA_LINK5A_TXIN2_N
FPGA_LINK5A_TXIN0_N
FPGA_LINK5A_TXIN0_P
FPGA_LINK5A_TXIN2_P
FPGA_LINK5A_TXIN3_P
FPGA_LINK5A_TXIN4_P
R10217
22
R10220
22
+3.3V_FPGA
L10205
L10206
OPT
C10204
4.7uF
10V
R10221
10K
OPT
C10213
0.1uF
IC10202
AOZ1072AI-3
EAN60922902
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
LX_1
8
LX_2
C10211
22uF
10V
+3.3V_NORMAL
L10207
CIC21J501NE
C10210
10uF
25V
R10223
27K
1%
R10225
14K
1%
+12V
R10222
20K
C10209
10uF
25V
C10215
100pF
50V
OPT
R10224
4.3K
1%
R10226
10K
L10209
3.6uH
NR8040T3R6N
C10214
2200pF
POWER_ON/OFF2_2
C10212
22uF
10V
L10208
CIC21J501NE
OPT
+2.5V_FPGA
IC10101
XC6SLX16-3CSG324I
IO_L62P_D5_2
R3
IO_L65P_INIT_B_2
U3
IO_L63P_2
T4
IO_L49P_D3_2
U5
IO_L48N_RDWR_B_VREF_2
T5
IO_L43N_2
V7
IO_L43P_2
U7
IO_L46N_2
T7
IO_L41N_VREF_2
V8
IO_L41P_2
U8
IO_L31N_GCLK30_D15_2
T8
IO_L30N_GCLK0_USERCCLK_2
V10
IO_L30P_GCLK1_D13_2
U10
IO_L29N_GCLK2_2
T10
IO_L23P_2
U11
IO_L16N_VREF_2
T11
IO_L14N_D12_2
V13
IO_L14P_D11_2
U13
IO_L3N_MOSI_CSI_B_MISO0_2
T13
IO_L12N_D2_MISO3_2
V14
IO_L12P_D1_MISO2_2
T14
IO_L1N_M0_CMPMISO_2
T15
IO_L2N_CMPMOSI_2
V16
IO_L2P_CMPCLK_2
U16
IO_L45N_2
V6
IO_L65N_CSO_B_2
V3
IO_L63N_2
V4
IO_L49N_D4_2
V5
IO_L32N_GCLK28_2
V9
IO_L45P_2
T6
IO_L23N_2
V11
IO_L62N_D6_2
T3
IO_L1P_CCLK_2
R15
IO_L3P_D0_DIN_MISO_MISO1_2
R13
IO_L13P_M1_2
N12
IO_L13N_D10_2
P12
IO_L16P_2
R11
IO_L29P_GCLK3_2
R10
IO_L31P_GCLK31_D14_2
R8
IO_L32P_GCLK29_2
T9
IO_L46P_2
R7
IO_L48P_D7_2
R5
IO_L64P_D8_2
N5
IO_L64N_D9_2
P6
VCCO_2_1
P9
VCCO_2_3
R12
VCCO_2_2
R6
VCCO_2_6
U14
VCCO_2_4
U4
VCCO_2_5
U9
L3101
CIS21J121
OPT
R3115
2.4K
+2.5V_FPGA
R3114
22
FPGA_SPI_CLK
R3113
1K
1/16W
1%
OPT
C3107
0.1uF
L3102
CIS21J121
FPGA_SPI_DO
FPGA_SPI_CZ
R3112
1.8K
FPGA_SPI_DI
R3116
1K
1/16W
1%
OPT
+3.3V_FPGA
IC3101
W25Q40CLSNIG
3
WP[IO2]
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD[IO3]
8
VCC
Decouplingcapacitors forVCCO Bank2
FPGA Bank_2 :
2.5V Power Rail should be applied.
Mode Pins --> determine configuration mode
Parallel configuration mode bus is auto-detected by the configuration logic.
M[1:0] = 10
CCLK Direction : Input
Bus Width : 8, 16
R2
Vout=0.8*(1+R1/R2)
TYPICAL ? mA
+2.5V_FPGA
R1
2A
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
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