THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FPGA_A_SDA
FPGA_A_SCK
FPGA_LINK2A_SMB_CS
I2C_SCL2
I2C_SDA2
FPGA_LINK1A_SMB_CS
AUD_SCK
FRC3_RESET
AUD_LRCH
AUD_LRCK
EXT_COMPENSATION_DONE
I2C_BE_SCL1
+3.3V_FPGA
+3.3V_FPGA
FPGA_LINK2A_TXCLKIN_N
FPGA_LINK2A_TXIN2_N
FPGA_LINK2A_TXIN3_N
FPGA_LINK2A_TXIN1_N
FPGA_LINK2A_TXIN0_N
FPGA_LINK2A_TXIN4_N
FPGA_LINK1A_TXIN2_N
FPGA_LINK1A_TXIN1_N
FPGA_LINK1A_TXIN4_N
FPGA_LINK1A_TXIN3_N
FPGA_LINK1A_TXIN0_N
FPGA_LINK1A_TXCLKIN_N
FPGA_LINK1A_TXCLKIN_P
FPGA_LINK1A_TXIN2_P
FPGA_LINK1A_TXIN1_P
FPGA_LINK1A_TXIN0_P
FPGA_LINK1A_TXIN3_P
FPGA_LINK1A_TXIN4_P
FPGA_LINK2A_TXCLKIN_P
FPGA_LINK2A_TXIN0_P
FPGA_LINK2A_TXIN1_P
FPGA_LINK2A_TXIN3_P
FPGA_LINK2A_TXIN2_P
FPGA_LINK2A_TXIN4_P
+2.5V_FPGA
+2.5V_FPGA
R10303
100
1/16W
1%
+2.5V_FPGA
R10301
0
R10302
0
OPT
C10306
0.01uF
R10304
33
1/16W
1%
C10303
0.47uF
25V
C10304
0.47uF
25V
C10305
0.47uF
25V
C10311
0.47uF
25V
C10309
0.47uF
25V
C10310
0.47uF
25V
AMP_MUTE
AMP_RESET_N
M_RFModule_RESET
R10305
0
M_REMOTE_TX
M_REMOTE_RX
M_RFModule_ISP
R10306
0
R10307
0
R10308
0
R10311
0
R10312
0
OPT
R10314
0
R10315
0
FPGA_XTAL_OUT
LINK1A_LOCK_N
C10301
10uF
16V
C10307
10uF
16V
R10317 0
OPT
R10316 0
OPT
IR
R10318
0
R10313
0
OPT
LINK2A_LOCK_N
LINK5A_LOCK_N
FPGA_XTAL_OUT
FPGA_LINK5A_SMB_CS
FPGA_LINK4A_SMB_CS
FPGA_LINK3A_SMB_CS
I2C_SCL3
I2C_SDA3
FPGA_DEBUG_1
FPGA_DEBUG_2
BACK_CHANNEL_LINK_READY
R10319
0
OPT
R10321
0
INV_CTL
R10323
0
OPT
OPTIC_GPIO1
BACK_CHANNEL_LINK_READY
OPTIC_BACK_CHANNEL
COMMERCIAL_12V_CTL
EL_VDD_ON_20V
EL_VDD_ON_20V
R103240
R103250
R103260
FPGA_LVDS_INFO
FRC3_FLASH_WP
AUD_MASTER_CLK
R10320
0
R103220
BACK_CHANNEL_P
R10218
10K
1/16W
1%
+2.5V_FPGA
C10313
0.1uF
R10219
10K
BACK_CHANNEL_N
C103140.1uF
I2C_BE_SDA1
C10302
4.7uF
10V
C10308
4.7uF
10V
R10338
0
OPT
R10339
0
OPT
I2C_SCL2
I2C_SDA2
Q10201
2N7002K
S
D
G
Q10202
2N7002K
S
D
G
R10340
0
OPT
R10341
0
OPT
+3.3V_FPGA
R10342
3.3K
R10343
3.3K
X10301
78.125MHz
4
VCC
1
EN/DIS
2
GND
3
OUTPUT
OPTIC_SERDES_RESET
C10312
5pF
50V
IC10101
XC6SLX16-3CSG324I
IO_L44N_A2_M1DQ7_1
J18
IO_L45N_A0_M1LDQSN_1
K18
IO_L45P_A1_M1LDQS_1
K17
IO_L41N_GCLK8_M1CASN_1
K16
IO_L44P_A3_M1DQ6_1
J16
IO_L42P_GCLK7_M1UDM_1
L15
IO_L41P_GCLK9_IRDY1_M1RASN_1
K15
IO_L36N_A8_M1BA1_1
H14
IO_L29P_A23_M1A13_1
C17
IO_L29N_A22_M1A14_1
C18
IO_L31P_A19_M1CKE_1
D17
IO_L31N_A18_M1A12_1
D18
IO_L33P_A15_M1A10_1
E16
IO_L33N_A14_M1A4_1
E18
IO_L35N_A10_M1A2_1
F18
IO_L35P_A11_M1A7_1
F17
IO_L1N_A24_VREF_1
F16
IO_L1P_A25_1
F15
IO_L38N_A4_M1CLKN_1
G18
IO_L38P_A5_M1CLK_1
G16
IO_L43N_GCLK4_M1DQ5_1
H18
IO_L43P_GCLK5_M1DQ4_1
H17
IO_L37N_A6_M1A1_1
H16
IO_L37P_A7_M1A0_1
H15
IO_L49N_M1DQ11_1
P18
IO_L49P_M1DQ10_1
P17
IO_L51P_M1DQ12_1
T17
IO_L52P_M1DQ14_1
U17
IO_L48N_M1DQ9_1
N18
IO_L48P_HDC_M1DQ8_1
N17
IO_L50N_M1UDQSN_1
N16
IO_L74P_AWAKE_1
P15
IO_L74N_DOUT_BUSY_1
P16
IO_L47N_LDC_M1DQ1_1
M18
IO_L47P_FWE_B_M1DQ0_1
M16
IO_L50P_M1UDQS_1
N15
IO_L53N_VREF_1
N14
IO_L46N_FOE_B_M1DQ3_1
L18
IO_L46P_FCS_B_M1DQ2_1
L17
IO_L42N_GCLK6_TRDY1_M1LDM_1
L16
IO_L51N_M1DQ13_1
T18
IO_L52N_M1DQ15_1
U18
IO_L30P_A21_M1RESET_1
F14
IO_L30N_A20_M1A11_1
G14
IO_L32P_A17_M1A8_1
H12
IO_L32N_A16_M1A9_1
G13
IO_L34P_A13_M1WE_1
K12
IO_L34N_A12_M1BA2_1
K13
IO_L36P_A9_M1BA0_1
H13
IO_L39P_M1A3_1
J13
IO_L39N_M1ODT_1
K14
IO_L40P_GCLK11_M1A5_1
L12
IO_L40N_GCLK10_M1A6_1
L13
IO_L53P_1
M14
IO_L61P_1
L14
IO_L61N_1
M13
VCCO_1_1
E17
VCCO_1_2
G15
VCCO_1_3
J14
VCCO_1_4
J17
VCCO_1_5
M15
VCCO_1_6
R17
IC10101
XC6SLX16-3CSG324I
IO_L33N_0
A8
IO_L39N_0
A11
IO_L41N_0
A12
IO_L37N_GCLK12_0
A10
IO_L35N_GCLK16_0
A9
IO_L62N_VREF_0
A14
IO_L64N_SCP4_0
A15
IO_L66N_SCP0_0
A16
IO_L4N_0
A3
IO_L6N_0
A5
IO_L8N_VREF_0
A6
IO_L5N_0
A4
IO_L10N_0
A7
IO_L1P_HSWAPEN_0
D4
IO_L1N_VREF_0
C4
IO_L2P_0
B2
IO_L2N_0
A2
IO_L3P_0
D6
IO_L3N_0
C6
IO_L4P_0
B3
IO_L5P_0
B4
IO_L6P_0
C5
IO_L10P_0
C7
IO_L8P_0
B6
IO_L11P_0
D8
IO_L11N_0
C8
IO_L33P_0
B8
IO_L34P_GCLK19_0
D9
IO_L34N_GCLK18_0
C9
IO_L35P_GCLK17_0
B9
IO_L36P_GCLK15_0
D11
IO_L36N_GCLK14_0
C11
IO_L37P_GCLK13_0
C10
IO_L38P_0
G9
IO_L38N_VREF_0
F9
IO_L39P_0
B11
IO_L41P_0
B12
IO_L62P_0
B14
IO_L63P_SCP7_0
F13
IO_L63N_SCP6_0
E13
IO_L64P_SCP5_0
C15
IO_L65P_SCP3_0
D14
IO_L65N_SCP2_0
C14
IO_L66P_SCP1_0
B16
VCCO_0_2
B10
VCCO_0_3
B15
VCCO_0_1
B5
VCCO_0_5
D13
VCCO_0_4
D7
VCCO_0_6
E10
Decouplingcapacitors forVCCO Bank1
Decouplingcapacitors forVCCO Bank0
This isFPGA_CLINK2.This is anoption.
Control signal input
From main
HEAD MICOM
-FRC & AMP
-FPGA & SERDES Rx/Tx
FPGA Bank_1 :
3,3V Power Rail should be applied.
FPGA Bank_0 :
2.5V Power Rail should be applied.
From MICOM
From L9 Main IC
Receive information from FPGA on DES boardvia ClearLink
MTK Test
To MICOM
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
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