RXBCLKP
RXA3N
RXA2N
RXA1N
+3.3V
RXB2P
RXACLKP
I2C_SDA_S
RXA1P
RXB2N
XTAL_OUT
TMS
RXB0N
+3.3V
SPI_DI
RXB4P
SPI_CS
XTAL_IN
TDI
RXBCLKN
TDO
RXB3N
RXB4N
XTAL_IN
FLASH_WP
UART_TX
RXA0P
SPI_SCLK
SPI_DI
SPI_DO
SPI_DO
UART_RX
SPI_CS
RXA4N
LG1122_RST
RXA0N
RXB3P
SPI_DL_MODE
RXB1N
SPI_SCLK
RXB1P
RXA4P
RXB0P
TRST_N
TCK
RXA2P
RXACLKN
I2C_SCL_S
RXA3P
XTAL_OUT
PWM_BPL
+3.3V
+3.3V
+3.3V
FRAME_OPT TCON_OPT
+3.3V
LG1122_TXBCLKP
LG1122_TXB1N
LG1122_TXD4P
LG1122_TXB2P
LG1122_TXA3P
LG1122_TXCCLKN
LG1122_TXC0P
LG1122_TXB3P
LG1122_TXD3N
LG1122_TXD2P
LG1122_TXB4P
LG1122_TXD2N
LG1122_TXB0P
LG1122_TXB4N
LG1122_TXD3P
LG1122_TXA0N
LG1122_TXC1P
LG1122_TXD1N
LG1122_TXA0P
LG1122_TXCCLKP
LG1122_TXA1P
LG1122_TXA1N
LG1122_TXB1P
LG1122_TXA4N
LG1122_TXC2N
LG1122_TXACLKN
LG1122_TXD0P
LG1122_TXB3N
LG1122_TXC3P
LG1122_TXDCLKN
LG1122_TXC0N
LG1122_TXC3N
LG1122_TXA2N
LG1122_TXBCLKN
LG1122_TXA3N
LG1122_TXD4N
LG1122_TXACLKP
LG1122_TXA2P
LG1122_TXC4N
LG1122_TXB0N
LG1122_TXD1P
LG1122_TXA4P
LG1122_TXB2N
LG1122_TXC1N
LG1122_TXC2P
LG1122_TXD0N
LG1122_TXC4P
LG1122_TXDCLKP
TCON_OPT
DISPLAY_OPT
SOC_OPT
REVERSE_OPT
FRAME_OPT
+3.3V+3.3V
SOC_OPT REVERSE_OPT
+3.3V
DISPLAY_OPT
OPT_READY_1
+3.3V
I2C_SCL_PQ
L/DIMMING_OPT
I2C_SDA_PQ
L/DIMMING_OPT
+3.3V
OPT_READY_1
+3.3V
3D_EN
OPT_READY_2
+3.3V
OPT_READY_2
FLASH_WP
LG1122_3DLR
LG1122_3DLR
TCON_I2C_EN
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
RXBCLKP
RXB2N
I2C_SCL_S
RXA1N
RXBCLKN
RXA2N
RXB1P
RXA3P
LG1122_RST
+3.3V
RXB4P
RXA4P
RXB3P
RXA2P
RXA0P
L/DIM0_VS
RXB2P
RXACLKP
RXB4N
RXA0N
RXB0N
RXA3N
PWM_BPL
L/DIM0_MOSI
RXB3N
I2C_SDA_S
L/DIM0_SCLK
RXA1P
RXB0P
FLASH_WP
+3.3V
RXA4N
RXACLKN
RXB1N
100
1%
R310
0.1uF
C306
33R329
3.3K
R302
10K
R357
10K
R355
MX25L3206EM2I-12G
IC301
3
WP#
2
SO/SIO1
4
GND
1
CS#
5
SI/SIO0
6
SCLK
7
HOLD#
8
VCC
10K
R360
4.7K
R356
33R325
OPT
33R339
OPT
3.3K
R303
100
1%
R344
33R340
OPT
100
1%
R318
4.7K
R353
3.3K
R309
10K
R368
33R349
33R332
OPT
27pF
50V
C305
33
OPT
R300
33R322
33R333
OPT
33R341
OPT
3.3K
R375
10K
OPT
R354
3.3K
R304
10K
R377
10K
R358
OPT
100
1%
R319
100
1%
R317
0R330
4.7K
R361
JTP-1127WEM
SW300
12
43
3.3K
R312
33R337
OPT
10uF
25V
C300
33R351
33R334
OPT
100
1%
R314
24.75MHz
X300
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
10KR328
10K
OPT
R373
10K
OPT
R369
33R321
10K
R374
100
1%
R316
33
OPT
R342
10K
R366
OPT
100
1%
R311
10K
R363
100
1%
R307
22R327
33R323
10K
R370
10K
R350
10K
OPT
R359
33R345
33
OPT
R301
0R331
33R338
OPT
33R336
OPT
47K
R352
1M
R372
10K
R371
OPT
22R326
33R335
3.3K
R305
33R347
0R308
33R346
100
1%
R306
27pF
50V
C304
100
1%
R343
10uF
25V
C301
LG1122
IC300
RXA0P
AC1
RXA0N
AC2
RXA1P
AB3
RXA1N
AC3
RXA2P
AB2
RXA2N
AB1
RXACLKP
AA1
RXACLKN
AA2
RXA3P
Y3
RXA3N
AA3
RXA4P
Y2
RXA4N
Y1
RXB0P
W1
RXB0N
W2
RXB1P
V3
RXB1N
W3
RXB2P
V2
RXB2N
V1
RXBCLKP
U1
RXBCLKN
U2
RXB3P
T3
RXB3N
U3
RXB4P
T2
RXB4N
T1
L_VSOUT_LD
B26
R_VSOUT_LD
E2
M0_SCLK
C26
M0_MOSI
E22
M1_SCLK
D24
M1_MOSI
G22
M2_SCLK
D2
M2_MOSI
E1
M3_SCLK
D1
M3_MOSI
D3
UART_RXD
G3
UART_TXD
H3
SPI_SCLK
G1
SPI_CS
G2
SPI_DI
F2
SPI_DO
F1
SDA_M
J1
SCL_M
J2
SDA_S
H1
SCL_S
H2
SMODE
K2
TMODE0
J3
TMODE1
K3
TMODE2
L3
TMODE3
M3
TRST_N
M2
TDO
L1
TDI
L2
TCLK
M1
TMS
N1
PORES_N
K1
XTALO
AF6
XTALI
AE6
MON_SYNC0
N2
MON_SYNC1
N3
MON_INTR
P3
VIREF_REXT
C1
TX_LOCKN
C2
GPIO[0]
AB5
GPIO[1]
AB4
GPIO[2]
AD5
GPIO[3]
AC5
GPIO[4]
AE4
GPIO[5]
AD4
GPIO[6]
AC4
GPIO[7]
AF3
GPIO[8]
AE3
GPIO[9]
AD3
GPIO[10]
AF2
GPIO[11]
AE2
GPIO[12]
AD2
GPIO[13]
AE1
GPIO[14]
B25
GPIO[15]
B24
TX0P
B2
TX0N
A2
TX1P
A3
TX1N
B3
TX2P
C4
TX2N
C3
TX3P
B4
TX3N
A4
TX4P
A5
TX4N
B5
TX5P
C6
TX5N
C5
TX6P
B6
TX6N
A6
TX7P
A7
TX7N
B7
TXA0P
A23
TXA0N
B23
TXA1P
C22
TXA1N
C23
TXA2P
B22
TXA2N
A22
TXACLKP
A21
TXACLKN
B21
TXA3P
C20
TXA3N
C21
TXA4P
B20
TXA4N
A20
TXB0P
A19
TXB0N
B19
TXB1P
C18
TXB1N
C19
TXB2P
B18
TXB2N
A18
TXBCLKP
A17
TXBCLKN
B17
TXB3P
C16
TXB3N
C17
TXB4P
B16
TXB4N
A16
TXC0P
A15
TXC0N
B15
TXC1P
C14
TXC1N
C15
TXC2P
B14
TXC2N
A14
TXCCLKP
A13
TXCCLKN
B13
TXC3P
C12
TXC3N
C13
TXC4P
B12
TXC4N
A12
TXD0P
A11
TXD0N
B11
TXD1P
C10
TXD1N
C11
TXD2P
B10
TXD2N
A10
TXDCLKP
A9
TXDCLKN
B9
TXD3P
C8
TXD3N
C9
TXD4P
B8
TXD4N
A8
GPIO[16]
C25
GPIO[17]
C24
GPIO[18]
AD1
GPIO[19]
R1
GPIO[20]
R2
GPIO[21]
R3
GPIO[22]
P1
GPIO[23]
A25
GPIO[24]
D23
GPIO[25]
D22
GPIO[26]
F22
GPIO[27]
E23
GPIO[28]
E3
GPIO[29]
F3
GPIO[30]
A24
GPIO[31]
P2
10K
R365
0R362
33R320
33R324
OPT
MLB-201209-0120P-N2
L300
10K
OPT
R364
33
OPT
R348
3.3K
R313
OPT
100
1%
R315
FI-RE51S-HF-J-R1500
P300
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
10K
OPT
R376
33
R367
PANEL_CTL
0.1uF
16V
C303
0.1uF
16V
C302
12507WR-08L
P302
1
2
3
4
5
6
7
8
9
L/D_R_DATA
33R380
L/D_R_CLK
L/D_R_V_SYNC
33R381
33R379
L/D_L_V_SYNC
L/D_L_CLK
33R378
L/D_L_DATA
12507WR-08L
P301
1
2
3
4
5
6
7
8
9
L/D_L_V_SYNC
L/D_R_V_SYNC
L/D_L_CLK
L/D_L_DATA
L/D_R_CLK
L/D_R_DATA
33R382
MDS62110215
M301
GASKET_FRC3
MDS62110215
M302
GASKET_FRC3
2N7002A
Q300
S
G
D
2N7002A
Q301
S
G
D
XTAL(24.75MHz)
RESET Input
1) LG1122_RST : From Main SOC
2) HW_RESET : From HW Switch
3) SPI_DL_MODE : Download Mode to Flash Mem
SPI FLASH(4MByte)
GPIO[1:0]
: Local Dimming Debugging
GPIO[7:3] = PWM[4:0]
1) GPIO[3] : 120Hz Mode --> 60 or 120Hz (Programmable)
240Hz Mode --> 120 or 240Hz (Programmable)
2) GPIO[4] : 120Hz Mode --> 60 or 120Hz (Programmable)
240Hz Mode --> 120 or 240Hz (Programmable)
3) GPIO[5] : 120Hz Mode --> 120 or 240Hz (Programmable)
240Hz Mode --> 240 or 480Hz (Programmable)
4) GPIO[6] : 120Hz Mode --> 120Hz (Fixed)
240Hz Mode --> 240Hz (Fixed)
5) GPIO[7] : 120Hz Mode --> 120Hz (Fixed)
240Hz Mode --> 240Hz (Fixed)
GPIO[8]
: External Vsync input for Local Dimming block
GPIO[10]
: T-Con L/R Sync Monitor(AR)
GPIO[12:11]
: S/W I2C_Master CH
GPIO[26:16]
: BLU Direct Control CH
GPIO[28:27]
: I2C for PQ tunning
I2C Slave Address
0x1C (Direct access)
0xB2 (In-direct access)
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
Will be deleted pull-up resistor from B0+3D Depth B’d
L/DIMMING_OPT
OPT
(for FRC3 JIG)
IMAGE_OPT
13
DISPLAY_OPT
L/D_ON_FRC
OPTION NAME
240Hz
OPT_READY_1
FRAME_OPT
HIGH
12
SOC_OPT
GPIO NO
OPT
OLED
LOW
OPT_READY_2
11
LCD
L/D_ON_MAIN
Default
Default
15
L9 (LG1152)
22
20
With_TCON
(for 72INCH)
Without_TCON
14
(for NON_72INCH)
MTK
IMAGE_NORMAL
120Hz
21
IMAGE_OPT
JIG_OPT
3 23
All of OPT decaps must be placed on PCB Bottom side
[51P HS-LVDS input wafer]
FRC3 & INPUT
2012.06.05EAX64768002
Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
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