LG F3000 - Page 103

- 104 -
B
MODEL
CLOSE TO ABB
71
Approved
6
D
INSERT
CLOSE TO MIC
2
KIM YOUNG GI
C
Notice No.
DRAWING
L
CLOSE TO EARJACK
2
4
REMOVE
2
5
LG Electronics Inc
.
3
(NROMCS2_GPIO44)
(GPIO_45)
NO.
43
A
8
(NGPCS1)
E
512Mbit Two Die
Name
A
10
5
Date
Date
MEMORY
(GPIO_9)
Iss.
2005
Section
(NRAMCS1)
9
B
3
B
Sheet/Sheets
(256 + 256NOR + 64 + 64PSRAM)
Checked
H
A
6
LG Electronics Inc.
5
LGIC(42)-A-5505-10:01
DRAWING
NAME
4
Sign & Name
LEE SEUNG YOON
Designer
1
1
D
C
12/01
LIM SANG HO
(NRAMCS2)
F3000
2 / 7
VER. 1.3
AUDIO/SOUND/MEMORY
(NROMCS1)
JACK_DETECT
(GPIO_40)
NA
C218
1uC238
C237
1u
R216
330K
R212
100
2.2K
C205
0.1u
R209
C202
10u
R210
1M
0R211
2V8_VEXT
C211
0.1u
J201
2V8_VMEM
2V5_JACK
C209
33u
39p
C217
R207
0.1u
C206
C1
GND
A1
B1
C2
A2
VCC
100
SN74AUC1G08YZPR
U206
2Y
C1
GND
D1
VCC
A2
VA205
EVL5M02200
SN74AUC2G08YZPR
U207
1A
A1
B1
1B
B2
1Y
D2
2A
2B
C2
MIC201
SOB-413S44-RC3310
1
2
C219
GND
1
NC
4
VOUT
32
Vin
39p
NCP563Q25T1
U201
33uC213
12K
R204
C221
2V8_VMEM
2V8_VEXT
NA
R200
1K
C216
R205
2.2K
39p
C236
EVL5M02200
1u
C220
VA204
39p
VA203
EVL5M02200
C203
NA
R206
NA
R208
2V8_VEXT
C200
0
0.1u
U202
2
GND
1
OUT
5
VCC
3
VIN+
VIN-
4
1K
R201
22u
C204
C210
39p
VA201
EVL5M02200
C207
0.1u
C231
0.1u
R214
2V5_VMIC
0
1.5K
R203
C212
39p
20K
R202
100R230
R226 330
R213 4.7
EVL5M02200
VA202
C208
NA
R215
1M
C215
39p
39p
C201
C234 1u
2V5_JACK
1uC235
E5
K1
_F1_CE
J2
_F1_OE
_F2_CE
G8
_F2_OE
H8
_F3_CE
K3
_F_RST
F4
F5
_F_WE
E4
_F_WP
_P1_CS
D6
K2
_P2_CS
_R_LB
C2
_R_OE
H1
_R_UB
F3
D5
_R_WE
J1
_S_CS1
P_MODE_CRE
P_VCC
K5
S_CS2
C5
S_VCC
K4
VCCQ0
L3
K7
VCCQ1
VCCQ2
J8
VSS0
L8
L7
VSS1
VSS2
L6
L5
VSS3
VSS4
L2
L1
VSS5
C4
VSS6
B4
VSS7
G7
WAIT
_ADV
D7
D8
G2
D9
J3
A1
DU0
A2
DU1 DU2
A7 A8
DU3 DU4
M1 M2
DU5
M7
DU6
M8
DU7
F1_VCC1
B5
L4
F1_VCC2
F2_VCC1
B6
K6
F2_VCC2
D4
F_VPP
K8
A8
A9
D7
CLK
C6
H2
D0
H3
D1
D10
G4
D11
J4
H5
D12
G6
D13
H6
D14
D15
J7
G3
D2
H4
D3
J5
D4
D5
G5
D6
J6
H7
A16
A17
D2
B2
A18
A19
B3
E1
A2
E6
A20
B7
A21
A22
C7
A23
C3
D3
A24
A25
E3
A3
D1
B1
A4
C1
A5
F2
A6
A7
E2
F6
PF38F4455LLZBQ0
U203
A0
G1
A1
F1
E7
A10
B8
A11
A12
C8
D8
A13
A14
F7
A15
E8
F8
DATA14
DATA15
DATA02
DATA03
DATA04
DATA05
DATA06
DATA07
DATA08
DATA09
_RESET
_WAIT
_ADV
CS1
CS2
_RD
_RESET
_WR
_RAM_CS1
_RAM_CS2
_LBS
_UBS
1V8_VCORE
ADD24
_ROM_CS2
CS2
_GPCS2
_GPCS1
CS1
AUXIP
HOOK_DETECTAUXIN
HEADSET_SPK_L
HEADSET_SPK_R
JACK_DETECT
BURSTCLK
DATA00
DATA01
DATA10
DATA11
DATA12
DATA13
VINNORP
VINNORN
ADD01
ADD03
ADD05
ADD07
ADD09
ADD11
ADD13
ADD15
ADD17
ADD19
ADD21
ADD23
ADD02
ADD04
ADD06
ADD08
ADD10
ADD12
ADD14
ADD16
ADD18
ADD20
ADD22
ADD24
_ROM_CS1
7. CIRCUIT DIAGRAM