LG FLATRON L2320A - Page 42

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Copyright 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Start/Stop
Logic
Slave Address
Comparator
Word Address
Pointer
Row
decoder
EEPROM
Cell Array
128 x 8 bits
256 x 8 bits
512 x 8 bits
HV Generation
Timing Control
Control Logic
Column Decoder
Data Register
DOUT and ACK
SCL
WP
SDA
A0
A1
A2
Figure 2-1. S524A40X10/40X20/40X40 Block Diagram