LG FLATRON L2320A - BLOCK DIAGRAM

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Copyright 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
SIL161BCT100
HS_DJTR
1
SiI 161B
100-Pin TQFP
(Top V iew)
PD
2
ST
3
PIXS
4
GND5
VCC
6
STAG_OUT7
SCDT
8
PDO
9
QE0
10
QE1
11
QE2
12
QE3
13
QE4
14
QE5
15
QE6
16
QE7
17
OVCC
18
OGND
19
QE8
20
QE9
21
QE1022
QE11
23
QE1224
QE13
25
QE14
26
QE15
27
OGND
28
OVCC
29
QE16
30
QE17
31
QE18
32
QE19
33
QE20
34
QE21
35
QE2236 QE23
37
VCC
38
GND
39
CTL1
40
CTL241 CTL3
42
OVCC
43
ODCK44 OGND
45
DE
46
VSYNC
47
HSYNC
48
QO049 QO1
50
75
QO21
74
QO20
73
QO19
72
QO18 71
QO17
70
QO16 69
GND
68
VCC
67
QO15
66
QO14
65
QO13
64
QO12
63
QO11
62
QO10
61
QO9
60
QO8
59
OGND
58
OVCC
57
QO7
56
QO6
55
QO5 54
QO4
53
QO3 52
QO2
51
QO22
OCK_INV
100
RESERVED
99
PGND
98
PVCC
97
EXT_RES
96
AV CC
95
RXC-
94
RXC+
93
AGND
92
RX0-
91
RX0+ 90
AGND
89
AV CC
88
AGND
87
RX1-
86
RX1+ 85
AV CC
84
AGND
83
AV CC 82
RX2-
81
RX2+
80
AGND
79
OVCC
78
QO23 77
OGND
76
DIFFERENTI AL SIGNAL
ODD 8-bits RED
EVEN 8-bits RED
ODD 8-bits GREEN
EVEN 8-bits GREEN
ODD 8-bits BLUE
EVEN 8-bits BLUE
CONFIG. PINS
PLL
PWR M ANAGEM ENT
GPO
OUTPUT CLOCK
CONTROLS
PIN CONFIGURATION
CTL3
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
SYNC2
EXT_RES
PDO
ST
ODCK
PIXS
HS_DJTR
OCK_INV
STAG_OUT
Data Recovery
CH2
VCR
Termination
Control
Data Recovery
CH1
VCR
Data Recovery
CH0
VCR
PLL
VCR
SYNC1
SYNC0
Channel
SYNC
SYNC2
SYNC1
SYNC0
Decoder
CTL2
CTL1
VSYNC
HSYNC
Panel
Inter-
face
Logic
QE[23:0]
24
QO[23:0]
24
DE
HSYNC
VSYNC
CTL3
CTL2
CTL1
SCDT
DATA
DATA
DATA
BLOCK DIAGRAM