LG lg-d821 - Page 216

5. BLOCK DIAGRAM
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Copyright © 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
[D821] Memory I/F
Main Chipset
(MSM8974)
DQ_0~31
HYNIX DDR3 SDRAM (PoP)
2GB (128M x 32 x 4CH), 800MHz
DQ0~31_a
SDC1_DATA_0~7
SanDisk 32GB eMMC 4.51
DATA0~7
CMD
CLK
SDC1_CMD
SDC1_CLK
CA_0~9
CA0~9_a
RESOUT_N
RESOUT_N
SDC2_DATA_0~3
SDC2_CMD
SDC2_CLK
EBI0
EBI1
SDC1
SDC2
Wi-Fi (BCM4335 CoB)
SDIO_DATA_0~3
SDIO_CMD
SDIO_CLK
DCLK / DCLKB
CK_a / CK_N_a
CKE_0~1
CKE0~1_a
CS0~1_N
DQS_0~3 / DQS_0B~3B
DM_0~3
ZQ
CS0~1_N_a
DQS0~3_t_a / DQS0~3_c_a
DM0~3_a
ZQ_a
DQ_0~31
DQ0~31_b
CA_0~9
CA0~9_b
DCLK / DCLKB
CK_b / CK_N_b
CKE_0~1
CKE0~1_b
CS0~1_N
DQS_0~3 / DQS_0B~3B
DM_0~3
ZQ
CS0~1_N_b
DQS0~3_t_b / DQS0~3_c_b
DM0~3_b
ZQ_b
CH_A (128M x 32 x 2)
CH_B (128M x 32 x 2)
10
32
10
32
8
4
eMMC_DATA[0]~[7]
eMMC_CMD
eMMC_CLK
MSM_RESOUT_N
WLAN_SDIO0~SDIO3
WLAN_CMD
WLAN_CLK
9. Memory I/F