LG PRADA KE850 - 7 Circuit Diagram

- 119 -
LGMC
VBAT
PWR
URXD
UTXD
3G 2.5G
GND
RX
TX
UFLS
ON_SW
LG Electronics
H
4
2
C
8
F
B
7
F
Page
6
C
12
R&D CHK :
5
Engineer :
Baseband Processor
1
G
E
4 10
DOC CTRL CHK :
V 1.0
7
10
12
H
Changed by: Time Changed:
Drawn by :
J-TAG
A
QA CHK:
E
HOLE
6
BASE BAND PROCESSOR
Ver.
11
11
Date Changed:
B
5
mentor 2005-10-11 3:07:35 pm
V1_Main
A3
12 1 8 A
MFG ENGR CHK :
2
1 / 4
ON BOARD ARM9 JTAG & ETM INTERFACE
9
Size:
G
A
1
8
9
3
D
TITLE:
3
D
1V5_Core
32.768KHz
12
TP102
VUSB
TP105
X101
0.1u
C109
TP108
R115 22
TP112
TP114
2V72_IO
0.1u
390K R107
C106
0.1u
C119
R112
NA
C120
1u
TP111
TP113
1V8_SD
1V8_SD
0.01u
C122
VMMC
1u
C116
1V5_DSP
0R120
P5
VSSP_ETM
T17
VSSVBR_1
VSSVBR_2
P17
VSSVBT
R16
VSS_DSPMAIN1
J8
VSS_DSPMAIN2
J9 J10
VSS_DSPMAIN3
J11
VSS_DSPMAIN4 VSS_DSPMAIN5
L8
VSS_DSPMAIN6
L9 L10
VSS_DSPMAIN7
L11
VSS_DSPMAIN8
VSS_PLL_RTC
T12 R12
VSS_USB
W11
VDD_USB
K16
VMICN VMICP
L16
P16
VREFN
L17
VREFP
VSSBB
L15
N19
VSSBG
U16
VSSD
V15
VSSM
VSSP_DIG1
J15 E13
VSSP_DIG2
E10
VSSP_DIG3 VSSP_DIG4
E8 J5
VSSP_EBU1 VSSP_EBU2
M5
VSSP_EBU3
R8
VDDP_MMC
A13 L19
VDDP_SIM
U18
VDDVBR_1
VDDVBR_2
R17
T15
VDDVBT
VDD_DSP1
H9 H10
VDD_DSP2
H11
VDD_DSP3
M9
VDD_MAIN1 VDD_MAIN2
M10
VDD_MAIN3
K8 K9
VDD_MAIN4
K10
VDD_MAIN5 VDD_MAIN6
K11
VDD_PLL
W12 W13
VDD_RTC
D9
USIF_SCLK USIF_TXD_MTSR
A7
VCXO_EN
K19
M15
VDDBB
VDDBG
K17
VDDD
T14
VDDM
V14
VDDP_DIGA
G19
VDDP_DIGB
A9 A15
VDDP_DIGC1
B19
VDDP_DIGC2
VDDP_DIGD
B1
VDDP_EBU1
J1
VDDP_EBU2
W2 W7
VDDP_EBU3
W10
VDDP_ETM
C18
T_OUT5
T_OUT6
D15
T_OUT7
D14
A18
T_OUT8
T_OUT9
C14
G3
USART0_CTS_N USART0_RTS_N
H4
USART0_RXD
G1 G4
USART0_TXD
F15
USART1_CTS_N USART1_RTS_N
E19
USART1_RXD
F17
G18
USART1_TXD
USB_DMINUS
V11
U11
USB_DPLUS
USIF_RXD_MRST
B7
TRACEPKT3
V9
U10
TRACEPKT4
TRACEPKT5
V10
R10
TRACEPKT6
TRACEPKT7
T11
U8
TRACESYNC
TRIG_IN
E14
TRST_N
C19
T_OUT0
B17
B16
T_OUT1
A16
T_OUT10
T_OUT11
C13
D17
T_OUT12
T_OUT2
B15
D13
T_OUT3
T_OUT4
B14
C17
RF_STR0
RF_STR1
A17
F18
RSTOUT_N
D18
RTCK
V12
RTC_OUT
SSC1_MRST
J17
K18
SSC1_MTSR
H15
SSC1_SCLK
E16
TCK
TDI
D19
E17
TDO
F16
TMS
TRACECLK
V8
R9
TRACEPKT0
TRACEPKT1
W9
T10
TRACEPKT2
U15
NC6
R11
NC7
L5
NC8
H5
NC9
V13
OSC32K
L12
PAOUT1A
PAOUT1B
M11
K12
PAOUT2A
PAOUT2B
J12
T9
PIPESTAT0
PIPESTAT1
U9
PIPESTAT2
W8
PM_INT
T13
RESET_N
U14
B18
RF_CLK
C16
RF_DATA
P19
MICN2
M17
MICP1 MICP2
N18
MMCI_CLK
C11
E12
MMCI_CMD
MMCI_DAT0
C12
D12
MMCI_DAT1
MMCI_DAT2
B12
MMCI_DAT3
A12
B13
MON1
MON2
A14
NC1
W19
NC2
W14 W1
NC3
A19
NC4 NC5
A1
F5
KP_IN3 KP_IN4
E3
KP_IN5
E2 E1
KP_IN6
D3
KP_OUT0 KP_OUT1
F4
KP_OUT2
C2 C1
KP_OUT3
M0
U17
W17
M1
M10
W18
M2
W16
W15
M7
M8
V16
V17
M9
MICN1
M18
I2S1_CLK1
G16
I2S1_RX
G17 G15
I2S1_TX
E18
I2S1_WA0 I2S2WA0
J19
I2S2WA1
H16
I2S2_CLK0
J18
I2S2_CLK1
H17 H19
I2S2_RX
H18
I2S2_TX
B2
IRDA_RX
IRDA_TX
A2
IREF
M16
KP_IN0
D2
KP_IN1
D1 D5
KP_IN2
P18
EPN11 EPN12
N17
EPP11
R19
T19
EPP12 EPPA11
T18
R18
EPPA12
V18
EPPA2
V19
EPREF1 EPREF2
U19
U12
F26M
F32K
U13
FCDP_RB_N
G2
K15
GUARD
C3
I2C_SCL
E4
I2C_SDA
F19
I2S1_CLK0
M3
EBU_BC0_N
EBU_BC1_N
P2
V3
EBU_BFCLKI
EBU_BFCLKO
R3
EBU_CAS_N
M4
EBU_CKE
T3
P4
EBU_CS0_N
EBU_CS1_N
V1
T2
EBU_CS2_N
P3
EBU_CS3_N
M2
EBU_RAS_N
EBU_RD_N
N3
U4
EBU_SDCLK1
EBU_SDCLKO
U3
EBU_WAIT_N
T6
U1
EBU_WR_N
R4
EBU_AD1
V6
EBU_AD10
EBU_AD11
W6
T8
EBU_AD12
EBU_AD13
U7
V7
EBU_AD14
EBU_AD15
R7
EBU_AD2
W3
T5
EBU_AD3
EBU_AD4
R6
U5
EBU_AD5
EBU_AD6
W4
W5
EBU_AD7
EBU_AD8
U6
EBU_AD9
V5
T7
EBU_ADV_N
EBU_A18
N2
N4
EBU_A19
EBU_A2
J4
EBU_A20
N5
T1
EBU_A21
EBU_A22
R2
U2
EBU_A23
V2
EBU_A24
J2
EBU_A3
J3
EBU_A4
EBU_A5
K1
K2
EBU_A6
EBU_A7
K3
K5
EBU_A8
EBU_A9
L2
EBU_AD0
V4
B3
DIF_VD
A3
DIF_WR
F3
DSP_IN0 DSP_IN1
G5
DSP_OUT0
F1 F2
DSP_OUT1
EBU_A0
H2
H3
EBU_A1
L1
EBU_A10
EBU_A11
M1
N1
EBU_A12
EBU_A13
K4
EBU_A14
L4
P1
EBU_A15
EBU_A16
L3
R1
EBU_A17
CLKOUT0
H1
DIF_CD
B5
DIF_CS1
A4
E6
DIF_CS2 DIF_D0
A6 C7
DIF_D1
B6
DIF_D2 DIF_D3
D8
DIF_D4
E7
A5
DIF_D5
D7
DIF_D6 DIF_D7
C6
DIF_HD
B4
DIF_RD
C5 D6
DIF_RESET1 DIF_RESET2
C4
L18
CC_IO
M19
CC_RST
E11
CIF_D0
B11
CIF_D1 CIF_D2
C10
CIF_D3
A11 D11
CIF_D4
B10
CIF_D5 CIF_D6
A10
CIF_D7
B9 A8
CIF_HSYNC
C9
CIF_PCLK
B8
CIF_PD
C8
CIF_RESET CIF_VSYNC
D10
CLKOUT
E9
PMB8876
U101
AFC
C15
AGND
N16
BB_I
R13
R14
BB_IX
P15
BB_Q
N15
BB_QX
CC_CLK
J16
C104
C125
0.1u
1V5_DSP
220n
0.1u
C123
1u
1V8_SD
1u
C110
C113
0.01u
OJ102
C115
TP106
TP101
2V65_ANA
NA
TP103
R119
0R117
C108
0.1u
C135C134
27p 27p
R113
3.3K
C131
100p
3.3K
R108 100K R109
1000p
C133
0.1u
C130
C126
15p
C114
0.1u
C101
0.1u
C118
0.01u
R105
0
TP110
2V72_IO
47K
R106
2V11_RTC
0.1u
C128
0.01u
100K
R122
C121
100p
C132
22KR116
0.1u
C129
C103
0.1u0.1u
C102C124
0.1u
1V8_SD
C112
0.01u
NA
R104
3
TX
6
VBAT
C107
0.1u
CTS
12
DSR
10
GND
1
NC1
4
7
NC2
NC3
8
9
NC4
5
ON_SW
11
RTS
RX
2
U102
VSUPPLY
0R118
2V85_SIM
47K
R121
R102
4.7
C117
0.1u
0.1u
C111
22R114
0R111
TP107
C127
15p
C105
TP104
0.1u
TP109
29
30
17
18
19
20
21
22
23
24
G1 G2
G3 G4
13
14
15
2
3
4
5
6
7
8
9
16
25
26
27
28
CN101
1
10
11
12
RF_TEMP
XO_ENE
KEYBACKLIGHT
KEYBACKLIGHT
FLASH_EN
TRIG_OUT
2V72_IO
1V5_Core
MM_WAIT
BT_RST
F_DPD
VC4
USB_EOC
26M_DAC
LCD_ID
JACK_DETECT
TF_PWR_EN
SNDOUT_R
SNDOUT_L
RCV_P
RCV_N
KP_IN5
HSMICN
HSMICP
DIF_RESET1
DIF_BYPASS
FM_SND_SEL
USB_CHG_EN
HOOK_DETECT
DSR
MON1
TDO
TMS
TCK
RTCK
TDI
TRSTn
TRIG_IN
TRIG_OUT
EXTRSTn
TRACEPKT7
TRACEPKT5
TRACEPKT3
TRACEPKT1
TRACECLK
TP_ATTN
REMOTE_INT
SPK_RCV_EN
RXD_0
RTS_0
DSR
TXD_0
VSUPPLY
REMOTE_ADC
TRACEPKT4
TRACEPKT6
TRACESYNC
PIPESTAT0
PIPESTAT1
PIPESTAT2
TRACEPKT0
TRACEPKT2
TF_DAT0
TF_DAT1
TF_DAT3
TF_CLK
TF_DETECT
USBDM
CTS_0
RPWRON
QX
Q
IX
I
AFC
MM_AD8
VMM_SHDN
MM_CS0
MM_A16
MM_RESET0
MM_AD7 MM_AD6 MM_AD5 MM_AD4 MM_AD3 MM_AD2 MM_AD1 MM_AD0
SIM_RST
SIM_IO
SIM_CLK
A10
A1
A0
FM_INT
SIM_EN_n
MM_WR
MM_RD
MM_INT
MM_AD15 MM_AD14 MM_AD13 MM_AD12 MM_AD11 MM_AD10
MM_AD9
A3
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
D3
D2
D15
D14
D13
D12
D11
D10
D1
D0
A9
A8
A7
A6
A5
A4
CS3n
CS_Flash2n
CS_RAM1n
CS_Flash1n
CKE
CASn
BFCLKI
BC1n
BC0n
ADVn
D9
D8
D7
D6
D5
D4
I2S2_TX
I2S2_CLK0
I2S2_WA0 I2S1_WA0
I2S1_TX
I2S1_RX
I2S1_CLK
SDA
SCL
26M_BB
WRn
WAITn
SDCLKI
RDn
RASn
MON2
TF_DAT2
TF_CMD
MICP
MICN
LOAD
BAT_ID
KP_OUT1 KP_OUT0
KP_IN4 KP_IN3 KP_IN2 KP_IN1 KP_IN0
TRACEPKT3
TRACEPKT2
TRACEPKT1
TRACEPKT0
TRACECLK
TMS
TDO
TDI
TCK
F_DPD
CLK32K
RTC_OUT
RTCK
EN
DA
CLK
RESETn
PM_INT
PIPESTAT2
PIPESTAT1
PIPESTAT0
PALEVEL
TX_DEBUG
RX_DEBUG
TXD_0
RXD_0
RTS_0
CTS_0
LCD_BACKLIGHT
MODE
VC3
VC2
VC1
RST_FM
VIBRATOR_EN
TXON_PA
TRSTn
TRIG_IN
TRACESYNC
TRACEPKT7
TRACEPKT6
TRACEPKT5
TRACEPKT4
SDCLKO
BFCLKO
JACK_TYPE
VMICP
XO_ENE
USIF_TXD
C_RPWRON
USIF_RXD
USBDP
7. CIRCUIT DIAGRAM