3. TECHNICAL BRIEF
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control pin VBIAS for efficiency enhancement. In GMSK mode, the PA is in saturated high efficiency
mode and is controlled via its VAPC pin directly by the baseband ramping DAC. In this way both up- /
down-ramping and output power level are set. In 8PSK mode, the ramping functionality is assured by
an on-chip ramping generator, whereas output power is controlled by the PGA’s as described above.
3.24. RF synthesizer
The transceiver contains a fractional-N sigma-delta synthesizer for the frequency synthesis in the RX
operation mode. For TX operation mode the fractional-N sigma-delta synthesizer is used as Sigma-
Delta modulation loop to process the phase/frequency signal. The 26MHz reference signal is provided
by the internal crystal oscillator. This frequency serves as comparison frequency of the phase detector
and as clock frequency for all digital circuitry.The divider in the feedback path of the synthesizer is
carried out as a multi-modulus divider (MMD). The loop filter is fully integrated and the loop bandwidth
is about 100 kHz to allow the transfer of the phase modulation. The loop bandwidth is automatically
adjusted prior to each slot (OLGA©˜). To overcome the statistical spread of the loop filter element
values an automatic loop filter adjustment (ALFA) is performed before each synthesizer startup. The
fully integrated quad-band VCO is designed for the four GSM bands (850, 900, 1800, 1900 MHz) and
operates at double or four times transmit or receive frequency. To cover the wide frequency range the
VCO is automatically aligned by a binary automatic band selection (BABS) before each synthesizer
startup.
3.25. VCTCXO
The VCTCXO (X401) supply 26MHz reference clock and controlled by AFC input to generate a strict
system clock. The 26MHz clock is used to Transceiver(U403), Bluetooth chip(U402) and S-Gold2
(U101).
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