LG RZ-50PY10 - Block Diagram

- 32 -
BLOCK DIAGRAM
RGB
(
PC/DTV
)
DVI
(
PC/DTV
)
RS232
IR
74ACT253
RX0/1,TX0/1
IR
TX
SCL/ SDA
RGB H/ V
SCL/ SDA
RX/ TX0/ 1/ 2, RX/ TXC
ST3232C
24LC21
74HCT0
8
24LC21
CXA2101
Scart1
Scart 2
Scart3
RF
CVBS
S-VHS
CXA2069Q
SWITCH
Tuner
(
M
)
Tuner
(
S
)
Vin1
(
CVBS
)
VPC3230
(
M
)
Video Decoder
VPC3230
(
S
)
Video Decoder
1H RGB Vin2
(
CVBS
)
MNT OUT
TV OUT
Vin3
(
CVBS
)
TU_Main
TU_Sub
Vin4 YCin4
Main_V
Main_YC
Main_V
Main_YC
SDA6001
Text Processor
Text_V
HYV641620
SRAM
AM29LV160
F-ROM
74LS123
Co m p _4 80i
M52758F
Switc h
S2300
DeInterlac er
YCbCr
/ 8
HY57V64322
SDRAM (8MB)
RGB PC/ DTV
RGB PC
RGB DTV
g m 1601
Sc aler ( Malibu)
Comp DTV
CXA_RGB
RGB_Dat a
Main_Video
/
24
Sub_Video
/ 8
DVI_Data
TX_Out
RS232_RX/ TX
Co mp/ RGB_SW
From Malibu
Dig it al
Analo g
Sid e - AV
CVBS S-VHS
Vin5
YCin5
Co m p _Y
Co mp _480I/ P
To Malib u
Video for TextText
TX0/ 1/ 2/ 3/ C Disp_En
SDATA
SCLK, SLE
HY5DU283 222A
SDRAM (128MB)
AM29LV
F-ROM
(
1MB
)
Co m p
/ RGB_SW
Co m p _4 80I/ P
Po s t- p ro c essing Bloc k is omit ted. so-c alled JEPICO, in this c as e
TMDS TX is also req uired . So und Pro ces sing Blo c k Diagram
is separated. .
RCA-type Blo c k Diagram is also
sep arated ..
DVI RX
w/ HDCP
ADC
w/ PLL
IEP
2424 2424
10
WIRE
ZHINE
Comp1
(
D
D/
D
T
V
)
V
BOARD
BOARD
BOARD
BLOCK DIAGRAM
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