M5Stack M5StickC - 3. FUNCTIONAL DESCRIPTION; 3.1 CPU and Memory; 3.2 Storage Description

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3
.1. CPU
S
P32-PICO-
m
prising:
448-KB
For a 5
2
KB RTC)
RTC fla
s
mode,
a
RTC slo
w
sleep m
Of 1 kb
i
set); th
e
include
3
.2. STO
.2.1. Ext
e
S
P32 supp
o
S
RAM), havi
a
ta.
ESP32 a
Flash c
o
access,
a
Up to 8
for 8-bi
t
suppor
t
E
SP32-PIC
O
p
ace, supp
o
S
P32 of, GP
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tegrated S
P
N
CTI
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p
ter descri
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AND
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s
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n
2
0 KB instru
c
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o
a
nd for stor
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memory,
ode
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t of eFuse,
w
e
remaining
encryption
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rnal Fla
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o
rt multiple
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o
de space is
a
nd can ex
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MB extern
a
t
, 16-bit an
d
t
s read and
w
O
-D4 4 MB
o
o
rt for 8-bit,
I
O7, GPIO8
,
P
I Flash, no
t
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b
es the ESP
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two low-
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d the prog
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f 8 KB SR
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i
ng data ac
c
of 8 KB SR
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w
hich is a
2
768 bit res
e
and chip I
D
D
ESCRI
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s
h and S
external Q
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are-based
A
n
al QSPI Fl
a
mapped i
n
e
cute code.
a
l Flash and
d
32-bit acc
w
rite opera
o
f integrate
d
16-bit and
,
GPIO9, GP
t
recomme
n
L
DES
C
3
2-PICO-D
4
R
Y
p
ower Xten
s
r
am starts f
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ata storage
A
M, when t
h
c
essed by t
h
A
M, can be
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56 bit syst
e
e
rved for u
s
D
P
TION
RAM
S
PI flash an
d
A
ES encryp
t
a
sh and SR
A
n
to the CPU
,
SRA
M ma
p
ess. Flash s
u
tions.
d
SPI Flash,
32-bit acc
e
IO10 and G
n
ded for ot
h
C
RIP
T
4
various m
o
s
a
®
32-bit L
X
o
r the kern
e
chip SRA
M
h
e RTC can
b
h
e main CP
U
a
ccessed b
y
e
m-specific
s
er progra
m
d
static ran
d
t
ion to prot
e
A
M by cachi
,
supports
8
p
ped to the
u
pports onl
the code c
a
e
ss, and can
PIO11 for c
h
er functio
n
T
ION
o
dules and
f
X
6 MCU. O
n
e
l function
c
M
(including
b
e started i
n
U
y
the copro
c
(MAC addr
e
m
, these Fl
a
d
om access
e
ct the use
r
ng. Up to 1
8
-bit, 16-bit
CPU data s
y read ope
r
a
n be map
p
execute c
o
onnecting
m
n
s.
f
unctions.
n
-chip me
m
c
alls
flash mem
o
n
Deep-sle
e
c
essor in D
e
e
ss and a c
h
a
sh progra
m
memory
r
programs
a
6 MB exter
n
and 32-bit
pace, supp
o
r
ations, SR
A
p
ed into CP
U
o
de. Pin GPI
O
m
odule
m
ory
o
ry 8
e
p
e
ep-
h
ip
m
a
nd
n
al
o
rt
A
M
U
O
6