Marantz SR7500/A1B - SiI 1161 IC Data (DVI PCB)

64
F
unctional Description
T
he SiI 1161 is a DVI 1.0 compliant PanelLink receiver in a compact package. It provides 24 or 48 bits for data
o
utput, and allows for panel support up to UXGA. Figure 1 shows the functional blocks of the chip.
PLL
Control Registers
-----------
Termination
and
Equalization
Control
Channel
SYNC
Data Recovery
CH2
Data Recovery
CH0
Data Recovery
CH1
VCR
Panel
Interface
Logic
RX2+
RX2-
RXC+
RXC-
RX0+
RX0-
RX1+
RX1-
PDO#
STAG_OUT#
ST
EXT_RES
OCK_INV
HS_DJTR
PIXS
VCR
VCR
VCR
SYNC2
SYNC1
SYNC0
Decoder
QE[23:0]
QO[23:0]
ODCK
DE
HSYNC
VSYNC
SCDT
CTL[3:1]
SDA
SCL
Figure 1. Functional Block Diagram
T
he PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
c
ore senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
t
he necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a DE signal that goes high when the active
r
egion of the video is present.
T
he SCDT signal is output when there is active video on the DVI link and the PLL in the TMDS has locked on to
t
he video. SCDT can be used to trigger external circuitry, indicating that an active video signal is present or used
t
o place the device in power down when no signal is present (by tying it to PDO#). The EXT_RES component is
u
sed for impedance matching.
IC11 IC12 (DVI PCB) : SiI 1161