Marantz SR7500/A1B - Page 58

78
Pin
Port
mode = 7
I/O Use STBY Name
Port Setting
Note
Act. init
IC36 (DSP PCB): H8S/2505(HD64F2505)
1 PE5 I/O I I HINBSY - - DSP Busy Signal
2 PE6 I/O O I AFDATA - L Analog Switch DATA
3 PE7 I/O O I AFCLK - L Analog Switch CLOCK
4 PD0 I/O O I CE_TCA H L Analog Switch TC9273
5 PD1 I/O O I CE_TCB H L Analog Switch TC9162/9163/9164
6 PD2 I/O O I MULTIMUTE H H MULTI ROOM MUTE
7 PD3 I/O O I SWMUTE H H SUB W MUTE
8 PD4 I/O O I CNTMUTE H H CENTER SP MUTE
9 PD5 I/O O I SBMUTE H H SRR B MUTE
10 PD6 I/O O I SL/SRMUTE H H SL SR MUTE
11 PD7 I/O O I L/RMUTE H H FRONT L R MUTE
12 Vss I - I VSS - - GND
13 PC0 I/O O I _RSTDAC L L DAC
14 P1Vcc I YES I VCC - - +5V'
15 PC1 I/O O I DFS H L DAC&ADC
16 PC2 I/O O I _ATT L H ADC
17 PC3 I/O O I _RSTADC L H ADC
18 PC4 I/O O I D_A - L DIR or _ADC sel
19 PC5 I/O I I XSTATE - - DIR
20 PC6 I/O O I _CEDIR L L DIR CHIP ENABLE
21 PC7 I/O O I _XMODE L L DIR RESET
22 PB0 I/O O O IICCLK - L I2C for E2PROM
23 PB1 I/O I/O I/O IICDATA - L I2C for E2PROM
24 PB2 I/O I I _TU_SD L Tuned
25 PB3 I/O I I TU_ST H Stereo Tune/_MONO
26 PB4 I/O O I TU_MUTE H H Tuner MUTE
27 PB5 I/O O I _CE_TU L L Tuner Pack
28 PB6 I/O O I N.C - L open
29 PB7 I/O I I _P_AMP_FAIL L - Power amp Dectect
30 PA0 I/O O I TUDOUT - L Tuner Pack
31 PA1 I/O O I TUCLK - L Tuner Pack
32 PA2 I/O I I TUDIN - Tuner Pack
33 PA3 I/O I I RDSDIN - Tuner Pack(RDS)
34 PA4 I/O O I VOLDATA - L Volume IC DATA
35 PA5 I/O O I VOLCLK - L Volume IC CLOCK
36 PA6 I/O O I CE_VOLA H L Volume IC Chip Sel A/B (TC9482)
37 PA7 I/O O I SB_ON H L SB Relay ControlSB ON:H SB OFF:L
38 PH7 I/O O I FLRA_ON H L SPK A SELECT
39 PH6 I/O O I FLRB_ON H L SPK B SELECT
40 PH5 I/O O I SURR_ON H L SURR/CNT SPK ON
41 PH4 I/O O I HEAT H ?L Power Amp+-B_L_Sel
42 PH3 I/O I I _HEAT_DET H - Power Amp Heat sink TempDetect
43 PH2 I/O O I _STANDBY L L Standby Power
44 PH1 I/O I I _HP_DET L - HP Jack Detect
45 PH0 I/O O I HP_ON H L HEAD PHONE ON
46 PJ7 I/O O I DVI_CONT2 DVI Input Control 2
47 PJ6 I/O O I DVI_CONT1 DVI Input Control 1
48 PJ5 I/O O I DVI_RX_PD2 DVI RX PowerDown Control 2
49 PJ4 I/O O I DVI_RX_PD1 DVI RX PowerDown Control 1
50 PJ3 I/O O I FPGA_RST L H DVI (FPGA Reset) This is not used.
51 PJ2 I/O O I DVI_TX_PD DVI TX PowerDown Control
52 PJ1 I/O O O _STBY LED L H Standby LED On
53 PJ0 I/O O I _RSFL L L Front FL Driver
54 Vss I - I VSS - - GND
55 P97/AN15/DA1 I,I,O I I - - PULL DOWN
56 P96/AN14/DA0 I,I,O I I - - PULL DOWN
57 P95/AN13 I,I I I CONF_DONE - - DVI (FPGA ROM Config)
58 P94/AN12 I,I I I SEL- - - Front Select Encoder
59 P93/AN11 I,I I I SEL+ - - Front Select Encoder
60 P92/AN10 I,I I I VOL- - - Front Vol. Encoder
61 P91/AN9 I,I I I VOL+ - - Front Vol. Encoder
62 P90/AN8 I,I I I _OVFL - - Peak Indicater
63 P47/AN7 I,I AD AD TV_AUTO - - TV Video Detect
64 P46/AN6 I,I AD AD MODE2 - - CPU mode2