Page 3
© 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 3
Architecture Highlights
l Single CPU integrating MCU & DSP functions
l Modified Harvard Bus Architecture:
l 3 operand instructions: A = B + C
l Extensive Addressing Modes
l 16 x 16-bit general purpose register set
l Fast, deterministic interrupt response
l Flexible software Stack with overflow detection
The dsPIC30F Central Processing Unit, or CPU, seamlessly integrates the best
features of a 16-bit MCU and DSP. Single instruction thread execution simplifies
application debug and ensures deterministic operation.
The dsPIC30F architecture is a modified Harvard Bus Architecture. This means that
the program and data memories are accessed by separate buses. However, there
are mechanisms to store and access constant data from the program memory
space. This enables more efficient use of the available on-chip memory for some
applications. Some instructions, specifically the dual-operand DSP instructions,
allow dual accesses from the data RAM during the same instruction cycle. This is of
tremendous benefit for DSP applications such as signal filtering.
The dsPIC30F provides a large number of addressing modes to ease code
development and enhance C compiler efficiency. Most addressing modes operate
orthogonally on a set of sixteen 16-bit general purpose registers, which means that
by and large, all instructions support all addressing modes.
Up to 45 individually vectored interrupt sources may be programmed to one of seven
priority levels. Fixed five cycle latency, from Interrupt Request to Interrupt Service
Routine entry, provides fast, deterministic application operation. The interrupt stack
is part of the on-chip RAM, and provides automatic bound checking to prevent
underflow or overflow.
To Next Page
Loading...
