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© 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 9
Instruction Set Overview
l 84 instructions (including DSC)
l Nearly all are one word (24 bits)
l Four are two words
l Most instructions execute in 1 Cycle, except:
l Program Flow Changes (2 cycles)
l TABLE instructions (2 cycles)
l Double Move Instructions (2 cycles)
l DO instruction (2 cycles)
l Divide instruction (18 cycles)
l Three operand instructions
l A = B op C
l Boosts code efficiency (assembly or C)
Let us now discuss the instruction set supported by the dsPIC30F
architecture.
The dsPIC30F CPU consists of 84 different instructions. If one
considers the various addressing modes possible, there are nearly 250
possible opcodes. Most of the instructions can be programmed in one
instruction word. However 4 instructions require an additional instruction
word; these are instructions such as Goto that involve specifying a 24-
bit program memory address.
Most instructions execute in one instruction cycle. The exceptions are
program flow changes, table instructions, double-word data moves, and
DO instructions which execute in two cycles. The divide instruction is
actually a single-cycle iterative instruction that needs to be repeated 18
times; the divide loop can be interrupted, however.
As noted earlier, the 24-bit instruction word enables three operand
instructions. This allows two source operands to be operated on, with
the result stored in a third location. This maximizes code efficiency in
both assembly and C language.
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