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© 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) 8
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SRAM Space
DSC-MAC Instructions View of
Data Memory Map - Example*
X Data Space
( SRAM )
0x0801 0x0800
0x17FE0x17FF
0x1801 0x1800
Y Data Space
( SRAM )
SFR Space
0x07FF 0x07FE
2 KB
SFR Space
0x27FF 0x27FE
0x0001 0x0000
MS Byte
Address
LS Byte
Address
16-bits
* Sample Data Memory
Map shown here for
dsPIC30F6014 device
0xFFFF
Unimplemented
X Data Space
0xFFFE
Optionally used by
mapping address
range into
Program Space
via PSV mechanism
0x8001 0x8000
There are some key differences between the addressing modes
supported by MAC-class instructions and those supported by all other
instructions. The MAC class of DSP instructions have the characteristic
that they operate on 2 source operands and can simultaneously
prefetch 2 words of data from RAM. A sample dsPIC30F6014 Data
Memory map is shown here as seen by MAC-class instructions.
The RAM is viewed as split X and Y data spaces for MAC-class DSP
instructions. In most devices, X and Y RAM are equal in size. This
partitioned view of the data space enables the MAC class of instructions
to perform simultaneous dual data fetch operations from memory, using
two independent data buses for X and Y RAM.
This partitioning of X and Y RAM is not user-configurable, but varies
from one device to another.
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