dsPIC33/PIC24 Family Reference Manual
DS30009711C-page 20 2006-2019 Microchip Technology Inc.
6.2 CN Configuration and Operation
The CN pins are configured as follows:
1. Ensure that the CN pin is configured as a digital input by setting the associated bit in the
TRISx register.
2. Enable interrupts for the selected CN pins by setting the appropriate bits in the CNENx
registers.
3. Turn on the weak pull-up devices (if desired) for the selected CN pins by setting the
appropriate bits in the CNPUx registers.
4. Clear the CNxIF interrupt flag.
5. Select the desired interrupt priority for CN interrupts using the CNxIP<2:0> control bits.
6. Enable CN interrupts using the CNxIE control bit.
When a CN interrupt occurs, the user should read the PORTx register associated with the CN
pin(s). This will clear the mismatch condition and set up the CN logic to detect the next pin
change. The current PORTx value can be compared to the PORT read value obtained at the last
CN interrupt to determine the pin that changed.
The CN pins have a minimum input pulse-width specification. Refer to the “Electrical
Characteristics” section of the specific device data sheet for further details.
6.3 CN Operation in Sleep and Idle Modes
The CN module continues to operate during Sleep or Idle mode. If one of the enabled CN pins
changes states, the CNxIF status bit will be set. If the CNxIE bit is set, the device will wake from
Sleep or Idle mode and resume operation.
If the assigned priority level of the CN interrupt is equal to, or less than, the current CPU priority
level, device execution will continue from the instruction immediately following the SLEEP or
IDLE instruction.
If the assigned priority level of the CN interrupt is greater than the current CPU priority level,
device execution will continue from the CN interrupt vector address.
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