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General| Brand | Microchip Technology |
|---|---|
| Model | dsPIC33 series |
| Category | Motherboard |
| Language | English |
Provides an introduction to the CAN FD protocol module.
Details the different CAN message frames used in CAN FD.
Lists the Special Function Registers (SFRs) used to control CAN FD operations.
Describes the various operational modes of the CAN FD protocol module.
Explains the configuration settings for the CAN FD module, including clock.
Covers the process of transmitting messages using CAN FD, including queues and FIFOs.
Details the behavior and configuration of the Transmit Event FIFO (TEF).
Explains the hardware filtering mechanism for receiving specific CAN FD messages.
Describes how messages are received and processed by the CAN FD module.
Explains the behavior of FIFOs and the Transmit Queue (TXQ) in the CAN FD module.
Details the timestamping capabilities of the CAN FD module using the Time Base Counter (TBC).
Explains the interrupt handling mechanisms within the CAN FD protocol module.
Covers the error detection, confinement, and recovery mechanisms of the CAN FD protocol.
Lists application notes related to the CAN FD protocol module.
Provides the revision history of the document, noting the initial version.
Outlines the key features of the CAN FD module, including general, FIFO, and transmission aspects.
Explains the difference between ISO and non-ISO CRC in CAN FD frames.
Details the configuration bits for the CAN Control Register High.
Details the configuration bits for the CAN Control Register Low.
Configuration for nominal bit time settings, including prescaler and time segments.
Configuration for nominal bit time settings, including time segments and synchronization jump width.
Configuration for data bit time settings, including prescaler and time segments.
Configuration for data bit time settings, including time segments and synchronization jump width.
Configuration for transmitter delay compensation modes and edge filtering.
Configuration for transmitter delay compensation offset and value bits.
Control register for the Time Base Counter (TBC) high bits.
Control register for the Time Base Counter (TBC) low bits.
Controls timestamping behavior, including reset, end-of-frame, and counter enable.
Controls timestamping behavior, including prescaler for the Time Base Counter.
Defines codes for receive and transmit interrupts.
Defines codes for filter hits and other interrupt events.
Enables various CAN interrupts, including message, mode, timer, and error interrupts.
Enables various CAN interrupts, including message, mode, timer, and error interrupts.
Status register for receive FIFO interrupt pending flags (high bits).
Status register for receive FIFO interrupt pending flags (low bits).
Status register for receive FIFO overflow interrupt pending flags (high bits).
Status register for receive FIFO overflow interrupt pending flags (low bits).
Status register for transmit FIFO/TXQ interrupt pending flags (high bits).
Status register for transmit FIFO/TXQ interrupt pending flags (low bits).
Status register for transmit attempt interrupt pending flags (high bits).
Status register for transmit attempt interrupt pending flags (low bits).
Controls message send requests for transmit objects (high bits).
Controls message send requests for transmit objects (low bits) and TXQ.
Defines the base address for transmit event FIFO and message objects.
Defines the base address for transmit event FIFO and message objects.
Controls TXQ payload size, FIFO size, retransmission attempts, and priority.
Controls TXQ reset, message send request, increment behavior, TX enable, and interrupts.
Provides status of the TXQ, including message index, aborted status, and pending interrupts.
Controls FIFO payload size, FIFO size, retransmission attempts, and priority for FIFOs 1-31.
Controls FIFO reset, message send request, increment behavior, TX/RX selection, and interrupts for FIFOs 1-31.
Provides status of FIFOs 1-31, including message index, aborted status, and pending interrupts.
Controls the FIFO size for the Transmit Event FIFO (TEF).
Controls TEF reset, timestamping, and interrupt enables for overflow, full, half-full, and not-empty conditions.
Provides status flags for the TEF, indicating overflow, full, half-full, and not-empty conditions.
Stores the user address for transmit/receive FIFO message objects (high bits).
Stores the user address for transmit/receive FIFO message objects (low bits).
Stores the user address for the next TEF object to be read (high bits).
Stores the user address for the next TEF object to be read (low bits).
Stores the user address for the next TXQ message object to be written (high bits).
Stores the user address for the next TXQ message object to be written (low bits).
Contains error count bits and error state indicators for transmit and receive operations.
Contains transmit and receive error counters.
Contains data bit rate transmit and receive error counters.
Contains nominal bit rate transmit and receive error counters.
Contains bits for various error types and an error-free message counter.
Contains error-free message counters for nominal and data bit rates.
Controls filter enable and points to the object for filters d (high bits).
Controls filter enable and points to the object for filters a and b (low bits).
Defines filter object bits, including extended identifier enable and standard identifier bits.
Defines filter object bits, including extended identifier bits and standard identifier bits.
Defines mask bits for filters, including identifier mode and standard/extended identifier masks.
Defines mask bits for filters, including standard and extended identifier masks.
Explains how to change the operating mode of the CAN FD module via register settings.
Describes the requirement to use Configuration mode for switching between Normal modes.
Describes the requirement to use Configuration mode for switching between Debug modes.
Explains that exiting Normal mode requires message transmission completion.
Details the process of entering and exiting Disable mode, including wake-up behavior.
Covers the conditions for entering the bus integrating state according to ISO11898-1:2015.
Details the different Normal modes of operation for the CAN FD module.
Describes the Normal CAN FD mode, allowing mixed CAN FD/2.0 messages and bit rate switching.
Describes the Normal CAN 2.0 mode, which only accepts Classic CAN 2.0 frames.
Explains the various debug modes for the CAN FD module.
Describes Listen Only mode for passive bus monitoring and baud rate detection.
Details Restricted Operation mode, which allows reception but limits transmission types.
Explains Loopback mode for internal message transmission testing without bus interaction.
Details the requirements and steps for entering Sleep mode, including prior Disable mode transition.
Explains Idle mode, its behavior based on the SIDL bit, and wake-up procedures.
Describes how the CAN module wakes up from Sleep mode, triggered by bus activity.
Explains clock source selection and configuration for the CAN FD module.
Explains how to enable ISO CRC for CAN FD frames.
Describes disabling protocol exception events and their impact on synchronization.
Explains the wake-up filter configuration for the CAN receive pin.
Details limiting retransmission attempts based on RTXAT and TXAT bits.
Explains how ESI bit behavior is configured for gateway applications.
Describes mode transition options (Restricted or Listen Only) upon system error.
Explains how to reserve RAM for TXQ and TEF by setting specific bits.
Defines the Synchronization Jump Width (SJW) and its role in resynchronization.
Discusses oscillator tolerance and provides conditions for maximum oscillator tolerance.
Provides an example of configuring bit time parameters for a CAN FD network.
Explains how to configure the TEF for RAM space, message count, and timestamping.
Details reserving RAM for TXQ, configuring message count, and payload size.
Explains configuring FIFOs as transmit buffers, setting message count, and payload size.
Explains configuring FIFOs as receive buffers, setting message count, payload size, and timestamping.
Provides formulas and examples for calculating the total RAM required for CAN FD message memory.
Specifies the fields within a transmit message object used by TXQ and transmit FIFOs.
Describes the process of loading messages into a transmit FIFO and updating pointers.
Explains loading messages into the TXQ, checking for space, and updating pointers.
Details how to initiate message transmission from a FIFO by setting TXREQ bits.
Explains how to initiate message transmission from the TXQ by setting the TXREQ bit.
Describes the C1TXREQ registers used for requesting transmissions from TXQ and TX FIFOs.
Explains how to configure transmit priority for FIFOs and the TXQ using TXPRIx bits.
Details how messages in the TXQ are prioritized based on their message ID.
Explains the goal of transmitting messages based on ID to avoid priority inversion.
Describes the bandwidth sharing feature and its configuration using TXBWS bits.
Covers configuring retransmission attempts, including disabling, three attempts, or unlimited.
Explains how to abort pending transmissions in FIFOs and the TXQ before SOF.
Describes the RTR mechanism for requesting data and its configuration for transmit FIFOs.
Details how the module handles mismatches between DLC and payload size during transmission.
Illustrates the state transitions for message queuing and transmission, including error handling.
Explains how to reset a transmit FIFO using FRESET or Configuration mode.
Explains how to reset the Transmit Queue using FRESET or Configuration mode.
Describes how to read TEF objects, check for emptiness, and calculate addresses.
Details methods for resetting the TEF, including FRESET and Configuration mode.
Describes configuring filters using C1FLTCON registers and enabling them with FLTEN bits.
Details the message filtering process after arbitration and control fields are received.
Explains how to configure filters to accept standard, extended, or both frame types.
Describes the use of mask objects to ignore selected bits of the received identifier.
Illustrates the detailed logic flow for matching a filter object to a received message.
Explains how DNCNT bits are used to compare data bytes with filter EID bits for standard frames.
Describes the 12-bit standard ID mode and its impact on filtering.
Specifies the contents of a receive message object, including ID, control bits, payload, and timestamp.
Describes how to read received messages from RX FIFOs and update pointers.
Explains how to reset an RX FIFO using FRESET or Configuration mode.
Details how the module handles mismatches between DLC and payload size during reception.
Provides a code example for receiving CAN FD extended frames and saving messages.
Details the transmit and receive FIFO status flags and their meanings.
Describes the status flags for transmit FIFOs (empty, half-empty, not full).
Describes the status flags for receive FIFOs (full, half-full, not empty).
Describes the status flags for the TXQ (empty, not full).
Describes the status flags for the TEF (full, half-full, not empty, overrun).
Explains the behavior of transmit FIFOs, including status flags and user address updates.
Explains the behavior of receive FIFOs, including status flags and user address updates.
Explains the behavior of the TXQ, including status flags and user address updates.
Specifies the reference points for CAN and CAN FD frame timestamping.
Illustrates the interrupt multiplexing structure from individual FIFO interrupts to main interrupts.
Details individual interrupts for FIFOs and the TXQ, including their sources and clearing mechanisms.
Explains TXQ interrupts (Not Full, Empty) and their sources.
Describes receive FIFO interrupts (Full, Half Full, Not Empty) and their sources.
Describes transmit FIFO interrupts (Not Full, Half Empty, Empty) and their sources.
Explains the RXOVIF interrupt when a FIFO is full and a message is received.
Explains the TXATIF interrupt when retransmission attempts fail.
Describes TEF interrupts (Full, Half Full, Not Empty, Overrun) and their sources.
Explains how individual FIFO interrupts are combined into status registers.
Details the main interrupts (RXIF, TXIF, RXOVIF, TXATIF, TEFIF) from combined FIFO interrupts.
Describes the IVMIF interrupt triggered by CAN bus errors or DLC mismatches.
Describes the WAKIF interrupt triggered by bus activity during Sleep mode.
Explains the CERRIF interrupt for CAN bus errors, including transitions to error passive and bus off states.
Describes the MODIF interrupt triggered by changes in the CAN module's operating mode.
Explains the TBCIF interrupt triggered by the Time Base Counter rollover.
Describes SERRIF interrupts for bus bandwidth errors and RX MAB overflows.
Explains efficient interrupt handling using lookup tables and status registers.
Details using C1VECL registers for implementing an interrupt lookup table.
Explains using combined interrupt status registers for efficient interrupt servicing.
Summarizes all interrupt flags, their registers, categories, and clearing methods.
Illustrates the different error states of the CAN FD Protocol Module.
Explains the process of recovering from the Bus Off state, including automatic recovery sequences.
