dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 42 2018 Microchip Technology Inc.
Register 3-42: C1TXQUAH: CAN Transmit Queue User Address Register High
(1)
R-x R-x R-x R-x R-x R-x R-x R-x
TXQUA<31:24>
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
TXQUA<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TXQUA<31:16>: TXQ User Address bits
A read of this register will return the address where the next message is to be written (TXQ head).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.
Register 3-43: C1TXQUAL: CAN Transmit Queue User Address Register Low
(1)
R-x R-x R-x R-x R-x R-x R-x R-x
TXQUA<15:8>
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
TXQUA<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TXQUA<15:0>: Transmit Queue User Address bits
A read of this register will return the address where the next message is to be written (TXQ head).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.