Microchip Technology dsPIC33 series User Manual

dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 92  2018 Microchip Technology Inc.
10.0 FIFO BEHAVIOR
This section explains the FIFO behavior when TEF and TXQ are enabled. FIFO 1 is configured
as a TX FIFO and FIFO 2 as an RX FIFO. The remaining FIFOs are not configured.
Table 10-1: Example FIFO Configuration
10.1 FIFO Status Flags
FIFO 1 through FIFO 31 can be configured as transmit or receive FIFOs. The same status flags
in C1FIFOSTAx are used for transmit and receive FIFOs. The status flags behave differently
based on the selected configuration.
10.1.1 TX FIFO STATUS FLAGS
There are three transmit status flags:
• TFEIF (TFE
RFFIF): Transmit FIFO Empty Interrupt Flag; set when the FIFO is empty.
• TFHIF (TFHRFHIF): Transmit FIFO Half Empty Interrupt Flag; set when FIFO is less than half full.
• TFNIF (TFNRFNIF): Transmit FIFO Not Full Interrupt Flag; set when FIFO is not full.
The status flags of a transmit FIFO are set when there is space to load a new message object
into the FIFO. Before the first message object is loaded (after the FIFO is reset), all status flags
are set. When the FIFO is fully loaded, all flags are cleared.
10.1.2 RX FIFO STATUS FLAGS
There are three receive status flags:
• RFFIF (TFERFFIF
): Receive FIFO Full Interrupt Flag; set when the FIFO is full.
• RFHIF (TFHRFHIF
): Receive FIFO Half Full Interrupt Flag; set when the FIFO is at least half full.
•RFNIF (TFNRFNIF): Receive FIFO Not Empty Interrupt Flag; set when there is at least one
message in the FIFO.
The status flags of the receive FIFO are set when there are received messages in the FIFO.
Before the first message is received (after the FIFO is reset), all status flags are cleared. When
the FIFO is full, all flags are set.
10.1.3 TXQ STATUS FLAGS
There are two TXQ status flags:
• TXQEIF: TXQ Empty Interrupt Flag; set when the TXQ is empty.
• TXQNIF: TXQ Not Full Interrupt Flag; set when TXQ is not full.
The status flags of the TXQ are set when there is space to load a new message object into the
TXQ. Before the first message object is loaded (after the TXQ is reset), all status flags are set.
When the TXQ is fully loaded, all flags are cleared.
Note 1: The start addresses are calculated based on the number of objects in the FIFO and
the PLSIZEx bits.
2: The start addresses of the FIFOs given in Table 10-1 are calculated when TEF
starts at 0x1400.
FIFO
Objects
in FIFO
Payload
per Object
Timestamp
Bytes in
Object
Bytes in
FIFO
Start Address
TEF 12 N/A Yes 12 144 0x1400
TXQ 8 32 N/A 40 320 0x1490
FIFO 1 5 64 N/A 72 360 0x15D0
FIFO 2 16 64 Yes 76 1216 0x1738
FIFO 3 N/A — — — — 0x1BF8

Microchip Technology dsPIC33 series Specifications

General

Brand	Microchip Technology
Model	dsPIC33 series
Category	Motherboard
Language	English